PLL103-04 データシートの表示（PDF） - PhaseLink Corporation

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PLL103-04

1-to-4 Clock Distribution Buffer

PhaseLink Corporation 

Preliminary PLL103-04

1-to-4 Clock Distribution Buffer

PIN DESCRIPTIONS

Name

FIN

CLK1

CLK2

CLK3

CLK4

GND

VDD

OE

Number

1

2

3

4

5

6

7

8

Type

I

O

O

O

O

P

P

I

Description

Input Clock Frequency (FIN range 0 ~ 160MHz).

Buffered Clock Output.

Buffered Clock Output.

Buffered Clock Output.

Buffered Clock Output.

Ground.

3.3V Power Supply.

Output Enable. Tri-states all outputs if low. Internal pull-up resistor of 30 kΩ

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 09/26/00 Page 2

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