PLL103-53XI データシートの表示（PDF） - PhaseLink Corporation
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PLL103-53XI Datasheet PDF : 7 Pages
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Preliminary PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
I2C BUS CONFIGURATION SETTING
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate Standard mode at 100kbits/s
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Bit 7
56
1
Bit 6
-
0
Bit 5
-
0
Enhance Drive Control
Bit 4
27,28,29,30
1
Bit 3
53, 52
1
Bit 2
51, 50
1
Bit 1
47, 46
1
Bit 0
42, 41
1
Description
SEL_DDR ( I2C is ready only, value is set through pin56 )
SDRAM Drive.
DDR Drive.
Bit6
Bit5
DDR Drive
SDRAM Drive
X
0
Enhanced 25%
Enhanced 25%
0
1
Normal
Normal
1
1
Normal
Enhanced 25%
DDR12T, DDR12C, DDR13T, DDR13C
DDR11T, DDR11C
DDR10T, DDR10C
DDR9T, DDR9C
DDR8T, DDR8C
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 3
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