PLL130-07 データシートの表示（PDF） - PhaseLink Corporation
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PLL130-07 Datasheet PDF : 5 Pages
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PLL130-07
High Speed Translator Buffer to CMOS (Selectable Drive)
PIN DESCRIPTION
Name
GND
VDD
DRIV_SEL
8pin SOIC
Pin number
1,3,6
4,7
8
3x3mm QFN
Pin number
1,2,4,5,
9,14,15
7,10,11,12
13
REF_IN
2
3
CLK_OUT
5
8
OE
N/A
16
Type
Description
P
Ground.
P
Power supply.
I
Drive Select input: ‘1’ for standard drive, ‘0’ for hi-drive output.
Internal pull-up (default is ‘1’).
I
Reference input signal. The frequency of this signal will be
reproduced at the output (after translation to CMOS level).
O
CMOS clock output.
I
Output enable (‘1’ for enable). Internal pull-up (default is ‘1’).
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD
4.6
V
VI
-0.5
VDD+0.5
V
VO
-0.5
VDD+0.5
V
TS
-65
150
°C
TA
-40
85
°C
TJ
125
°C
260
°C
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
Input Frequency
Input signal swing
Output Frequency
CONDITIONS
REF_IN input
MIN. TYP. MAX. UNITS
0
200
MHz
100
mV
0
200
MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2
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