PLL130-69 データシートの表示（PDF） - PhaseLink Corporation
部品番号
コンポーネント説明
メーカー
PLL130-69 Datasheet PDF : 5 Pages
| |||
PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
3. AC Specifications
PARAMETERS
Input Frequency
Input signal swing
Output Frequency
CONDITIONS
REFIN input
MIN. TYP. MAX. UNITS
0
1000 MHz
100
mV
0
1000 MHz
4. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
5. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
VDD – 1.025
VDD – 1.810
MAX.
VDD – 0.880
VDD – 1.620
UNITS
V
V
MIN. TYP. MAX. UNITS
0.2
0.5
ns
0.2
0.5
ns
PECL Levels Test Circuit
OUT
VDD
50Ω
2.0V
PECL Output Skew
OUT
50%
50Ω
OUT
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 3
Share Link: 