PLS153A データシートの表示（PDF） - Philips Electronics

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PLS153A

Programmable logic arrays(18 ×42 ×10)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic arrays

(18 × 42 × 10)

Product specification

PLS153/A

TIMING DIAGRAM

I, B

1.5V

1.5V

+3V

1.5V

0V

VOH

B

1.5V

VT

1.5V

VOL

tPD

tOD

tOE

SP00279

LOGIC PROGRAMMING

The PLS153/A is fully supported by industry

standard (JEDEC compatible) PLD CAD

tools, including Philips Semiconductors

SNAP, Data I/O’s ABEL™ and Logical

Devices, Inc. CUPL™ design software

packages.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

PLS153/A logic designs can also be

generated using the program table entry

format detailed on the following page. This

program table entry format is supported by

the Philips Semiconductors SNAP PLD

design software package.

To implement the desired logic functions, the

state of each logic variable from logic

equations (I, B, O, P, etc.) is assigned a

symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,

are defined below.

PROGRAMMING/SOFTWARE

SUPPORT

Refer to Section 9 (Development Software)

and Section 10 (Third-Party Programmer/

Software Support) of this data handbook for

additional information

OUTPUT POLARITY – (B)

S

X

S

B

B

X

ACTIVE LEVEL

HIGH1

(NON–INVERTING)

CODE

H

AND ARRAY – (I, B)

I, B

I, B

I, B

I, B

ACTIVE LEVEL

LOW

(INVERTING)

CODE

L

SP00280

I, B

I, B

I, B

I, B

I, B

STATE

INACTIVE1, 2

P, D

CODE

O

STATE

I, B

P, D

CODE

H

STATE

I, B

P, D

CODE

L

I, B

I, B

I, B

STATE

DON’T CARE

P, D

CODE

–

SP00281

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.

October 22, 1993

6

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