PLUS405-55A データシートの表示（PDF） - Philips Electronics

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PLUS405-55A

Programmable logic sequencer (16 × 64 × 8)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic sequencer

(16 × 64 × 8)

Product specification

PLUS405-55

DESCRIPTION

The PLUS405-55 device is a bipolar,

programmable state machine of the Mealy

type. Both the AND and the OR array are

user-programmable. All 64 AND gates are

connected to the 16 external dedicated inputs

(I0 - I15) and to the feedback paths of the

8 on-chip State Registers (QP0 - QP7). Two

complement arrays support complex

IF-THEN-ELSE state transitions with a single

product term (input variables C0, C1).

All state transition terms can include True,

False and Don’t Care states of the controlling

state variables. All AND gates are merged

into the programmable OR array to issue the

next-state and next-output commands to their

respective registers. Because the OR array is

programmable, any one or all of the 64

transition terms can be connected to any or

all of the State and Output Registers.

All state (QP0 - QP7) and output (QF0 - QF7)

registers are edge-triggered, clocked J-K

flip-flops, with Asynchronous Preset and

Reset options. The PLUS405 architecture

provides the added flexibility of the J-K toggle

function which is indeterminate on S-R

flip-flops. Each register may be individually

programmed such that a specific

Preset-Reset pattern is initialized when the

initialization pin is raised to a logic level “1”.

This feature allows the state machine to be

asynchronously initialized to known internal

state and output conditions prior to

proceeding through a sequence of state

transitions. Upon power-up, all registers are

unconditionally preset to “1”. If desired, the

initialization input pin (INIT) can be converted

to an Output Enable (OE) function as an

additional user-programmable feature.

Availability of two user-programmable clocks

allows the user to design two independently

clocked state machine functions consisting of

four state and four output bits each.

Order codes are listed in the Ordering

Information Table below.

FEATURES

• 66.7MHz minimum guaranteed clock rate

• 55MHz minimum guaranteed operating

frequency (1/(tIS1 + tCKO1)

• Functional superset of PLS105/105A

• Field-programmable (Ti-W fusible link)

• 16 input variables

• 8 output functions

• 64 transition terms

• 8-bit State Register

• 8-bit Output Register

• 2 transition Complement Arrays

• Multiple clocks

• Programmable Asynchronous Initialization

or Output Enable

• Power-on preset of all registers to “1”

• “On-chip” diagnostic test mode features for

access to state and output registers

• 950mW power dissipation (typ.)

• TTL compatible

• J-K or S-R flip-flop functions

• Automatic “Hold” states

• 3-State outputs

APPLICATIONS

• Interface protocols

• Sequence detectors

• Peripheral controllers

• Timing generators

• Sequential circuits

• Elevator contollers

• Security locking systems

• Counters

• Shift registers

PIN CONFIGURATIONS

N Package

CLK 1

I7 2

I6 3

I5/CLK 4

I4 5

I3 6

I2 7

I1 8

I0 9

F7 10

F6 11

F5 12

F4 13

GND 14

28 VCC

27 I8

26 I9

25 I10

24 I11

23 I12

22 I13

21 I14

20 I15

19 INIT/OE

18 F0

17 F1

16 F2

15 F3

N = Plastic DIP (600mil-wide)

A Package

I5/CLK I6 I7 CLK VCC I8 I9

4 3 2 1 28 27 26

I4 5

25 I10

I3 6

24 I11

I2 7

23 I12

I1 8

22 I13

I0 9

21 I14

F7 10

20 I15

F6 11

19 INIT/OE

12 13 14 15 16 17 18

F5 F4 GND F3 F2 F1 F0

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION

28-Pin Plastic Dual In-Line (600mil-wide)

28-Pin Plastic Leaded Chip Carrier

OPERATING

FREQUENCY

55MHz (tIS + tCKO)

55MHz (tIS + tCKO)

ORDER CODE

PLUS405–55N

PLUS405–55A

DRAWING NUMBER

0413B

0401F

October 22, 1993

180

853–1546 11164

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