PM5351-BI データシートの表示（PDF） - PMC-Sierra
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PM5351-BI Datasheet PDF : 393 Pages
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S/UNI-TETRA
DATASHEET
PMC-1971240
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
13.3 PACKET OVER SONET/SDH DATA STRUCTURE ......................................358
13.4 BIT ERROR RATE MONITOR.....................................................................358
13.5 CLOCKING OPTIONS ...............................................................................359
13.6 LOOPBACK OPERATION..........................................................................361
13.7 JTAG SUPPORT........................................................................................369
13.7.1
TAP CONTROLLE R.................................................................370
13.7.1.1 STATES ......................................................................372
13.7.1.2 INSTRUCTIONS ..........................................................373
13.8 BOARD DESIGN RECOMMENDATIONS ....................................................374
13.9 ANALOG POWER SUPPLY FILTERING......................................................375
13.10 POWER SUPPLIES SEQUENCING............................................................380
13.11 INTERFACING TO ECL OR PECL DEVICES...............................................382
13.12 CLOCK RECOVERY LOOP FILTER...........................................................385
13.13 SETTING THE S/UNI-TETRA IN ATM MODE ..............................................385
13.14 SETTING THE S/UNI-TETRA IN POS MODE ..............................................386
13.15 SETTING THE S/UNI-TETRA FOR SONET OR SDH APPLICATIONS ..........387
13.16 USING THE S/UNI-TETRA WITH A 5 VOLT ODL.........................................387
FUNCTIONAL TIMING ...........................................................................................388
14.1 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE.............................................388
14.2 PACKET OVER SONET/SDH (POS) SYSTEM INTERFACE.........................390
14.3 SECTION AND LINE DATA COMMUNICATION CHANNELS ........................393
ABSOLUTE MAXIMUM RATINGS...........................................................................396
D.C. CHARACTERISTICS ......................................................................................397
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................400
A.C. TIMING CHARACTERISTICS .........................................................................404
18.1 SYSTEM RESET TIMING...........................................................................404
18.2 REFERENCE TIMING................................................................................404
18.3 ATM SYSTEM INTERFACE TIMING ...........................................................405
18.4 POS SYSTEM INTERFACE TIMING ...........................................................409
18.5 LINE AND SECTION DCC TIMING.............................................................414
18.6 TRANSMIT AND RE CEIVE FRAME PULSES..............................................416
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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