PM6670STR データシートの表示（PDF） - STMicroelectronics

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PM6670STR

Complete DDR2/3 memory power supply controller

STMicroelectronics 

Pin settings

PM6670S

2.2

Pin description

Table 2. Pin functions

N°

Pin

Function

1

VTTGND LDO power ground. Connect to negative terminal of VTT output capacitor.

2

VTTSNS

LDO remote sensing. Connect as close as possible to the load via a low

noise PCB trace.

DDR voltage selector (if MODE is tied to VCC) or pulse-skip/no-audible

3

DDRSEL pulse-skip selector in adjustable mode (MODE voltage lower than 3 V). See

Section 7.1.4: Mode-of-operation selection on page 30.

4

VTTREF

Low noise buffered DDR reference voltage. A 22 nF (minimum) ceramic

bypass capacitor is required in order to achieve stability.

Ground reference for analog circuitry, control logic and VTTREF buffer.

5

SGND

Connect together with the thermal pad and VTTGND to a low impedance

ground plane. See the Application Note for details.

6

AVCC

+5 V supply for internal logic. Connect to +5 V rail through a simple RC

filtering network.

High accuracy output voltage reference (1.237 V) for multilevel pins setting.

7

VREF

It can deliver up to 50 μA. Connect a 100 nF capacitor between VREF and

SGND in order to enhance noise rejection.

Frequency selection. Connect to the central tap of a resistor divider to set

8

VOSC

the desired switching frequency. The pin cannot be left floating. See

Section 7: Device description on page 20

VDDQ output remote sensing. Discharge path for VDDQ in Non-Tracking

9

VSNS

Discharge. Input for internal resistor divider that provides VDDQ/2 to

VTTREF and VTT. Connect as close as possible to the load via a low noise

PCB trace.

Mode of operation selector. If MODE pin voltage is higher than 4 V, the fixed

10

MODE

output mode is selected. If MODE pin voltage is lower than 4 V, it is used as

negative input of the error amplifier. See Section 7.1.4: Mode-of-operation

selection on page 30.

11

COMP

DC voltage error compensation Input for the switching section. Refer

Section 7.1.4: Mode-of-operation selection on page 30.

12

DSCG

Discharge mode selection. Refer to Section 7.1.8: VDDQ output discharge

on page 34 for tracking/non-tracking discharge or no-discharge options.

Switching controller enable. Connect to S5 system status signal to meet S0-

13

S5

S5 power management states compliance. See Section 7.3: S3 and S5

power management pins on page 38, S5 pin can't be left floating.

Linear regulator enable. Connect to S3 system status signal to meet S0-S5

14

S3

power management states compliance. See Section 7.3: S3 and S5 power

management pins on page 38, S3 pin can't be left floating.

15

PG

Power Good signal (open drain output). High when VDDQ output voltage is

within ±10 % of nominal value.

16

PGND

Power ground for the switching section.

17

LGATE Low-side gate driver output.

6/54

Doc ID 14432 Rev 4

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