PM7830 データシートの表示（PDF） - PMC-Sierra

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PM7830

Baseband Radio Interface Controller

PMC-Sierra 

PM7830 BRIC

Baseband Radio Interface Controller

PRODUCT OVERVIEW

The PM7830 Baseband to Radio Interface Controller (BRIC) is a full-

featured 6-port termination device that fully supports the CPRI specifi-

cation for wireless base station interconnection. The BRIC provides

integrated rate-adaptive SERDES links along with CPRI framing,

mapping, switching, and combining functions.

When used in conjunction with the 2-port PM7832 BRIC-2, the BRIC

and BRIC-2 can be used to flexibly create scalable CPRI-compliant

distributed architectures.

PRODUCT HIGHLIGHTS

• Operates in all of the following Baseband-to-RF interconnect

topologies:

• Local interconnect using a central combiner/distributor topology.

• Local interconnect using a full mesh topology.

• Remote interconnect using a point-to-point (P2P) star topology.

• Remote interconnect using a tree and branch topology.

• Remote interconnect using a chain topology.

• Remote interconnect using a ring topology.

Advance

Product Brief

• Supports up to 6 serial channels running independently at CPRI line

rates from 614.4 Mbit/s to 2457.6 Mbit/s with 8B/10B-encoded

data.

• Supports up to 6 parallel Radio Bus Interfaces (RBIs) for output of

user data.

• Supports CPRI start-up sequence and link-rate auto-negotiation for

both REC and RE operating modes.

• Supports traffic switching at the CPRI Antenna Carrier (AxC) level.

• Supports IQ summing.

• Supports multiplexing and termination of control and

synchronization sub-channels:

• Up to 6 Ethernet Fast C&M channels.

• Up to 6 HDLC Slow C&M channels.

• Measures round-trip delay on each CPRI link with an accuracy of

±1 ns:

• Provides programmable delay insertion to meet CPRI delay

calibration requirements.

• Supports serial line protection switching.

• Supports configuration, control, monitoring and test capability on a

per-channel basis.

BLOCK DIAGRAM

MPIF

SYNC HDLC

6 x RMII/SMII JTAG

Clock

Synthesis

Unit

(CSU)

Microprocessor

Interface

(MPIF)

Synchronization

& HDLC

Processor

(SCHP)

JTAG

6 x Tx Serial

Link Data

6 x Rx Serial

Link Data

Rate Adaptive

SERDES

Link #0

Link #1

Link #2

Link #3

Link #4

Link #5

Radio Frame Mapper

(RMAP)

Radio Frame

Demapper (RDMP)

Ctrl. & Mgmt.

Processor

(CMP)

6 x Parallel

Radio Bus

Interface

(RBI)

Delay Calculator

Crossbar With Summing (XCSUM)

PMC-2051672, Issue 1

© Copyright PMC-Sierra, Inc. 2005

All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.

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