DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PM8315 データシートの表示(PDF) - PMC-Sierra

部品番号
コンポーネント説明
メーカー
PM8315 Datasheet PDF : 330 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
STANDARD PRODUCT
DATASHEET
PMC-1981125
ISSUE 7
PM8315 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
FIGURE 98 - SBI DROP BUS COLLISION AVOIDANCE TIMING ............... 291
FIGURE 99 - H-MVIP EGRESS DATA & FRAME PULSE TIMING............... 293
FIGURE 100 - H-MVIP INGRESS DATA TIMING ........................................... 294
FIGURE 101 - XCLK INPUT TIMING.............................................................. 295
FIGURE 102 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP
ENABLED MODE...................................................................... 297
FIGURE 103 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING MODE ................................................................... 298
FIGURE 104 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE................................................................. 299
FIGURE 105 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
CLEAR CHANNEL MODE......................................................... 300
FIGURE 106 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
SERIAL DATA AND HMVIP CCS MODE ................................... 301
FIGURE 107 - EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE...................................................................... 302
FIGURE 108 - INGRESS INTERFACE TIMING - CLOCK SLAVE MODES ... 304
FIGURE 109 - INGRESS INTERFACE TIMING - CLOCK MASTER MODES 305
FIGURE 110 - TRANSMIT LINE INTERFACE TIMING .................................. 306
FIGURE 111 - REMOTE SERIAL ALARM PORT TIMING.............................. 308
FIGURE 112 - JTAG PORT INTERFACE TIMING.......................................... 310
FIGURE 113 - 324 PIN PBGA 23X23MM BODY ............................................ 312
LIST OF TABLES
TABLE 1
TABLE 2
- E1-FRMR FRAMING STATES .................................................. 75
- PATH SIGNAL LABEL MISMATCH STATE ............................. 105
PROPRIETARY AND CONFIDENTIAL
x

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]