ADM1020 データシートの表示（PDF） - Analog Devices

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ADM1020

8-Lead, Low-Cost, System Temperature Monitor

Analog Devices 

ADM1020–SPECIFICATIONS (TA = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted)

Parameter

Min Typ Max

Units Test Conditions/Comments

POWER SUPPLY AND ADC

Temperature Resolution

1

Temperature Error, Local Sensor

–3

Temperature Error, Remote Sensor

–3

–5

Supply Voltage Range

3

Undervoltage Lockout Threshold

2.5

Undervoltage Lockout Hysteresis

Power-On Reset Threshold

0.9

POR Threshold Hysteresis

Standby Supply Current

Average Operating Supply Current

Auto-Convert Mode, Averaged Over 4 Seconds

Conversion Time

65

Remote Sensor Source Current

D– Source Voltage

Address Pin Bias Current

±1

+3

+3

+5

3.6

2.7 2.95

25

1.7 2.2

50

3

10

4

70

190

160 290

115 170

90

5.5

0.7

50

°C

Guaranteed No Missed Codes

°C

°C

°C

TA = +60°C to +100°C

°C

V

Note 1

V

VDD Input, Disables ADC,

Rising Edge

mV

V

VDD, Falling Edge2

mV

µA

VDD = 3.3 V, No SMBus Activity

µA

SCLK at 10 kHz

µA

0.25 Conversions/Sec Rate

µA

2 Conversions/Sec Rate

ms From Stop Bit to Conversion

Complete (Both Channels)

D+ Forced to D– + 0.65 V

µA

High Level

µA

Low Level

V

µA

Momentary at Power-On Reset

SMBUS INTERFACE

Logic Input High Voltage, VIH

STBY, SCLK, SDATA

Logic Input Low Voltage, VIL

STBY, SCLK, SDATA

SMBus Output Low Sink Current

ALERT Output Low Sink Current

Logic Input Current, IIH, IIL

SMBus Input Capacitance, SCLK, SDATA

SMBus Clock Frequency

SMBus Clock Low Time, tLOW

SMBus Clock High Time, tHIGH

SMBus Start Condition Setup Time, tSU:STA

SMBus Repeat Start Condition

Setup Time, tSU:STA

SMBus Start Condition Hold Time, tHD:STA

SMBus Stop Condition Setup Time, tSU:STO

SMBus Data Valid to SCLK

Rising Edge Time, tSU:DAT

SMBus Data Hold Time, tHD:DAT

SMBus Bus Free Time, tBUF

SCLK Falling Edge to SDATA

Valid Time, tVD,DAT

2.2

0.8

6

1

–1

+1

5

0

100

4.7

4

4.7

250

4

4

250

0

4.7

1

V

VDD = 3 V to 5.5 V

V

VDD = 3 V to 5.5 V

mA SDATA Forced to 0.6 V

mA ALERT Forced to 0.4 V

µA

pF

kHz

µs

tLOW Between 10% Points

µs

tHIGH Between 90% Points

µs

ns

Between 90% and 90% Points

µs

Time from 10% of SDATA to

90% of SCLK

µs

Time from 90% of SCLK to 10%

of SDATA

ns

Time from 10% or 90% of

SDATA to 10% of SCLK

µs

µs

Between Start/Stop Condition

µs

Master Clocking in Data

NOTES

1Operation at VDD = +5 V guaranteed by design, not production tested.

2Guaranteed by design, not production tested.

Specifications subject to change without notice.

–2–

REV. 0

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