TE28F008BE-B120 データシートの表示（PDF） - Intel

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TE28F008BE-B120

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

E

3.3.4.1

Suspending and Resuming Erase

Since an erase operation requires on the order of

seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in

order to read data from another block of the

memory. Once the erase sequence is started,

writing the Erase Suspend command to the CUI

requests that the WSM pause the erase sequence

at a predetermined point in the erase algorithm. The

status register will indicate if/when the erase

operation has been suspended.

At this point, a Read Array command can be written

to the CUI in order to read data from blocks other

than that which is being suspended. The only other

valid command at this time is the Erase Resume

command or Read Status Register command.

3.4.2

WP# = VIL FOR BOOT BLOCK

LOCKING

When WP# = VIL, the boot block is locked and

program/erase operations to the boot block will

result in an status register error. All other blocks

remain unlocked and can be programmed or erased

normally. Note that this feature is overridden and

the boot block unlocked when RP# = VHH. Since

the WP# pin is not available on the 44-PSOP, the

boot block’s default status is locked when RP# is at

VIH or VIL. See Section 3.4.4 for additional

information on unlocking on the 8-Mbit 44-PSOP

package.

3.4.3

RP# = VHH OR WP# = VIH FOR BOOT

BLOCK UNLOCKING

During erase suspend mode, the chip can go into a

pseudo-standby mode by taking CE# to VIH, which

reduces active current draw.

To resume the erase operation, enable the chip by

taking CE# to VIL, then issuing the Erase Resume

command, which continues the erase sequence to

completion. As with the end of a standard erase

operation, the status register must be read, cleared,

and the next instruction issued in order to continue.

3.4 Boot Block Locking

The boot block family architecture features a

hardware-lockable boot block so that the kernel

code for the system can be kept secure while the

parameter and main blocks are programmed and

erased independently as necessary. Only the boot

block can be locked independently from the other

blocks. The truth table, Table 9, clearly defines the

write protection methods.

3.4.1

VPP = VIL FOR COMPLETE

PROTECTION

For complete write protection of all blocks in the

flash device, the VPP programming voltage can be

held low. When VPP is below VPPLK, any program or

erase operation will result in a error in the status

register.

Two methods can be used to unlock the boot block:

1. WP# = VIH

2. RP# = VHH

If both or either of these two conditions are met, the

boot block is unlocked and can be programmed or

erased. See Section 3.4.4 for additional information

on unlocking on the 8-Mbit 44-PSOP package.

3.4.4

NOTE FOR 8-MBIT 44-PSOP

PACKAGE

The 8-Mbit in the 44-PSOP does not have a WP#

because no other pins were available for the 8-Mbit

upgrade address. Thus, in this density-package

combination only, VHH (12 V) on RP# is required to

unlock the boot block and unlocking with a logic-

level signal is not possible. If this unlocking

functionality is required, and 12 V is not available

in-system, consider using the 48-TSOP package,

which has a WP# pin and can be unlocked with a

logic-level signal. All other density-package

combinations have WP# pins.

Table 9. Write Protection Truth Table

VPP

VIL

≥ VPPLK

≥ VPPLK

RP#

X

VIL

VHH

WP#

X

X

X

Write Protection

All Blocks Locked

(Reset)

All Blocks Unlocked

≥ VPPLK VIH VIL Boot Block Locked

≥ VPPLK VIH VIH All Blocks Unlocked

NOTE: WP# not available on 44-PSOP. In this pkg., treat

as if WP# is tied low, eliminating the last row of this table.

22

SEE NEW DESIGN RECOMMENDATIONS

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