TE28F008BE-B120 データシートの表示（PDF） - Intel
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TE28F008BE-B120 Datasheet PDF : 58 Pages
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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
E
Start
Write 20H,
Block Address
Write D0H and
Block Address
Read Status
Register
0
SR.7 =
Suspend Erase
Loop
NO
Suspend YES
Erase
1
Full Status
Check if Desired
Bus
Operation
Command
Comments
Write
Erase Setup
Data = 20H
Addr = Within Block to Be Erased
Write
Read
Erase
Confirm
Data = D0H
Addr = Within Block to Be Erased
Status Register Data Toggle CE#
or OE# to Update Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to reset device to read array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.4,5 =
0
1
SR.5 =
0
Block Erase Successful
24
VPP Range Error
Command Sequence
Error
Bus
Operation Command
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 7. Automated Block Erase Flowchart
0539_07
SEE NEW DESIGN RECOMMENDATIONS
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