TE28F008BE-B120 データシートの表示（PDF） - Intel

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TE28F008BE-B120

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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1.2 Main Features

Intel’s SmartVoltage technology is the most flexible

voltage solution in the flash industry, providing two

discrete voltage supply pins: VCC for read

operation, and VPP for program and erase

operation. Discrete supply pins allow system

designers to use the optimal voltage levels for their

design. All products (28F800BV/CV, 28F008BV,

28F800CE and 28F008BE) provide program/erase

capability at 5 V or 12 V. The 28F800BV/CV and

28F008BV allow reads with VCC at 3.3 ± 0.3 V or

5 V, while the 28F800CE and 28F008BE allow

reads with VCC at 2.7 V–3.6 V or 5 V. Since many

designs read from the flash memory a large

percentage of the time, 2.7 V VCC operation can

provide great power savings. If read performance is

an issue, however, 5 V VCC provides faster read

access times. For program and erase operations,

5 V VPP operation eliminates the need for in system

voltage converters, while 12 V VPP operation

provides faster program and erase for situations

where 12 V is available, such as manufacturing or

designs where 12 V is in-system. For design

simplicity, however, just hook up VCC and VPP to

the same 5 V ± 10% source.

The 28F800/28F008B boot block flash memory

family is a high-performance, 8-Mbit (8,388,608 bit)

flash memory family organized as either

512 Kwords of 16 bits each (28F800 only) or

1024 Kbytes of 8 bits each (28F800 and 28F008B).

Separately erasable blocks, including a hardware-

lockable boot block (16,384 bytes), two parameter

blocks (8,192 bytes each) and main blocks (one

block of 98,304 bytes and seven blocks of 131,072

bytes) define the boot block flash family

architecture. See Figures 4 and 5 for memory

maps. Each block can be independently erased and

programmed 100,000 times at commercial

temperature or 10,000 times at extended

temperature.

The boot block is located at either the top (denoted

by -T suffix) or the bottom (-B suffix) of the address

map in order to accommodate different

microprocessor protocols for boot code location.

The hardware-lockable boot block provides

complete code security for the kernel code required

for system initialization. Locking and unlocking of

the boot block is controlled by WP# and/or RP#

(see Section 3.4 for details).

The Command User Interface (CUI) serves as the

interface between the microprocessor or

microcontroller and the internal operation of the

boot block flash memory products. The internal

Write State Machine (WSM) automatically executes

the algorithms and timings necessary for program

and erase operations, including verifications,

thereby unburdening the microprocessor or

microcontroller of these tasks. The Status Register

(SR) indicates the status of the WSM and whether it

successfully completed the desired program or

erase operation.

Program and erase automation allows program and

erase operations to be executed using an industry-

standard two-write command sequence to the CUI.

Data writes are performed in word (28F800 family)

or byte (28F800 or 28F008B families) increments.

Each byte or word in the flash memory can be

programmed independently of other memory

locations, unlike erases, which erase all locations

within a block simultaneously.

The 8-Mbit SmartVoltage boot block flash memory

family is also designed with an Automatic Power

Savings (APS) feature which minimizes system

battery current drain, allowing for very low power

designs. To provide even greater power savings,

the boot block family includes a deep power-down

mode which minimizes power consumption by

turning most of the flash memory’s circuitry off. This

mode is controlled by the RP# pin and its usage is

discussed in Section 3.5, along with other power

consumption issues.

Additionally, the RP# pin provides protection

against unwanted command writes due to invalid

system bus conditions that may occur during

system reset and power-up/down sequences. For

example, when the flash memory powers-up, it

automatically defaults to the read array mode, but

during a warm system reset, where power

continues uninterrupted to the system components,

the flash memory could remain in a non-read mode,

such as erase. Consequently, the system Reset

signal should be tied to RP# to reset the memory to

normal read mode upon activation of the Reset

signal (see Section 3.6).

The 28F800 provides both byte-wide or word-wide

input/output, which is controlled by the BYTE# pin.

Please see Table 2 and Figure 13 for a detailed

description of BYTE# operations, especially the

usage of the DQ15/A–1 pin.

6

SEE NEW DESIGN RECOMMENDATIONS

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