E28F008BV-B70 データシートの表示（PDF） - Intel

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E28F008BV-B70

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

E

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

4.2.1

APPLYING VCC VOLTAGES

When applying VCC voltage to the device, a delay

may be required before initiating device operation,

depending on the VCC ramp rate. If VCC ramps

slower than 1V/100 µs (0.01 V/µs) then no delay is

required. If VCC ramps faster than 1V/100 µs (0.01

V/µs), then a delay of 2 µs is required before

initiating device operation. RP# = GND is

recommended during power-up to protect against

spurious write signals when VCC is between VLKO

and VCCMIN.

VCC Ramp Rate

Required Timing

≤ 1V/100 µs

No delay required.

> 1V/100 µs

A delay time of 2 µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay is

measured beginning from the time VCC reaches VCCMIN (3.0 V for 3.3 ± 0.3 V operation;

and 4.5 V for 5 V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3 V and 5 V operation, the system should first transition VCC from the existing voltage range to GND,

and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations

pending or in progress.

3. These guidelines must be followed for any VCC transition from GND.

4.3 Capacitance

TA = 25 °C, f = 1 MHz

Symbol

Parameter

Notes

Typ

Max

CIN

Input Capacitance

1

6

8

COUT

Output Capacitance 1, 2

10

12

NOTES:

1. Sampled, not 100% tested.

2. For the 28F008B, address pin A10 follows the COUT capacitance numbers.

Units

pF

pF

Conditions

VIN = 0 V

VOUT = 0 V

SEE NEW DESIGN RECOMMENDATIONS

29

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