28F002BV データシートの表示（PDF） - Intel

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28F002BV

2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

E

2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION

Flash memory combines EPROM functionality with

in-circuit electrical program and erase. The boot

block flash family utilizes a Command User

Interface (CUI) and automated algorithms to

simplify program and erase operations. The CUI

allows for 100% TTL-level control inputs, fixed

power supplies during erasure and programming,

and maximum EPROM compatibility.

When VPP < VPPLK, the device will only successfully

execute the following commands: Read Array,

Read Status Register, Clear Status Register and

intelligent identifier mode. The device provides

standard EPROM read, standby and output disable

operations. Manufacturer identification and device

identification data can be accessed through the CUI

or through the standard EPROM A9 high voltage

access (VID) for PROM programming equipment.

The same EPROM read, standby and output

disable functions are available when 5 V or 12 V is

applied to the VPP pin. In addition, 5 V or 12 V on

VPP allows program and erase of the device. All

functions associated with altering memory contents:

Program and Erase, Intelligent Identifier Read, and

Read Status are accessed via the CUI.

The internal Write State Machine (WSM) completely

automates program and erase, beginning operation

signaled by the CUI and reporting status through

the status register. The CUI handles the WE#

interface to the data and address latches, as well

as system status requests during WSM operation.

3.1 Bus Operations

Flash memory reads, erases and programs in-

system via the local CPU. All bus cycles to or from

the flash memory conform to standard

microprocessor bus cycles. These bus operations

are summarized in Tables 3 and 4.

3.2 Read Operations

3.2.1

READ ARRAY

When RP# transitions from VIL (reset) to VIH, the

device will be in the read array mode and will

respond to the read control inputs (CE#, address

inputs, and OE#) without any commands being

written to the CUI.

When the device is in the read array mode, five

control signals must be controlled to obtain data at

the outputs.

• RP# must be logic high (VIH)

• WE# must be logic high (VIH)

• BYTE# must be logic high or logic low

• CE# must be logic low (VIL)

• OE must be logic low (VIL)

In addition, the address of the desired location must

be applied to the address pins. Refer to Figures 15

and 16 for the exact sequence and timing of these

signals.

If the device is not in read array mode, as would be

the case after a program or erase operation, the

Read Mode command (FFH) must be written to the

CUI before reads can take place.

During system design, consideration should be

taken to ensure address and control inputs meet

required input slew rates of <10 ns as defined in

Figures 12 and 13.

SEE NEW DESIGN RECOMMENDATIONS

15

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