271092-005 データシートの表示（PDF） - Intel

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271092-005

80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION

Intel 

M80C287

Data Types

Table 1 lists the seven data types that the M80C287

supports and presents the format for each type Op-

erands are stored in memory with the least signifi-

cant digit at the lowest memory address Programs

retrieve these values by generating the lowest ad-

dress For maximum system performance all oper-

ands should start at physical-memory addresses

that correspond to the word size of the CPU oper-

ands may begin at any other addresses but will re-

quire extra memory cycles to access the entire oper-

and

Internally the M80C287 holds all numbers in the ex-

tended-precision real format Instructions that load

operands from memory automatically convert oper-

ands represented in memory as 16- 32- or 64-bit

integers 32- or 64-bit floating-point numbers or 18-

digit packed BCD numbers into extended-precision

real format Instructions that store operands in mem-

ory perform the inverse type conversion

Numeric Operands

A typical NPX instruction accepts one or two oper-

ands and produces one (or sometimes two) results

In two-operand instructions one operand is the con-

tents of an NPX register while the other may be a

memory location The operands of some instructions

are predefined for example FSQRT always takes

the square root of the number in the top stack ele-

ment

Register Set

Figure 2 shows the M80C287 register set When an

M80C287 is present in a system programmers may

use these registers in addition to the registers nor-

mally available on the CPU

DATA REGISTERS

M80C287 computations use the M80C287’s data

registers These eight 80-bit registers provide the

equivalent capacity of 20 32-bit registers Each of

the eight data registers in the M80C287 is 80 bits

wide and is divided into ‘‘fields’’ corresponding to

the NPX’s extended-precision real data type

The M80C287 register set can be accessed either

as a stack with instructions operating on the top one

or two stack elements or as individually addressable

registers The TOP field in the status word identifies

the current top-of-stack register A ‘‘push’’ operation

decrements TOP by one and loads a value into the

new top register A ‘‘pop’’ operation stores the value

from the current top register and then increments

TOP by one The M80C287 register stack grows

‘‘down’’ toward lower-addressed registers

Instructions may address the data registers either

implicitly or explicitly Many instructions operate on

the register at the TOP of the stack These instruc-

tions implicitly address the register at which TOP

points Other instructions allow the programmer to

explicitly specify which register to use This explicit

register addressing is also relative to TOP

TAG WORD

The tag word marks the content of each numeric

data register as Figure 3 shows Each two-bit tag

represents one of the eight data registers The prin-

cipal function of the tag word is to optimize the

NPX’s performance and stack handling by making it

possible to distinguish between empty and nonemp-

ty register locations It also enables exception han-

dlers to identify special values (e g NaNs or denor-

mals) in the contents of a stack location without the

need to perform complex decoding of the actual

data

STATUS WORD

The 16-bit status word (in the status register) shown

in Figure 4 reflects the overall state of the M80C287

It may be read and inspected by programs

Bit 15 the B-bit (busy bit) is included for M8087

compatibility only It always has the same value as

the ES bit (bit 7 of the status word) it does not

indicate the status of the BUSY output of M80C287

Bits 13 – 11 (TOP) point to the M80C287 register that

is the current top-of-stack

The four numeric condition code bits (C3 – C0) are

similar to the flags in a CPU instructions that per-

form arithmetic operations update these bits to re-

flect the outcome The effects of these instructions

on the condition code are summarized in Tables 2

through 5

Bit 7 is the error summary (ES) status bit This bit is

set if any unmasked exception bit is set it is clear

otherwise If this bit is set the ERROR signal is as-

serted

Bit 6 is the stack flag (SF) This bit is used to distin-

guish invalid operations due to stack overflow or un-

derflow from other kinds of invalid operations When

SF is set bit 9 (C1) distinguishes between stack

overflow (C1e1) and underflow (C1e0)

3

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