MC80287 データシートの表示（PDF） - Intel

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MC80287

80-BIT HMOS NUMERIC PROCESSOR EXTENSION

Intel 

M80287

SYSTEM CONFIGURATION WITH

M80286

As a processor extension to an M80286 the

M80287 can be connected to the CPU as shown in

Figure 4 The data channel control signals (PEREQ

PEACK) the BUSY signal and the NPRD NPWR

signals allow the NPX to receive instructions and

data from the CPU When in the protected mode all

information received by the NPX is validated by the

M80286 memory management and protection unit

Once started the M80287 can process in parallel

with and independent of the host CPU When the

NPX detects an error or exception it will indicate this

to the CPU by asserting the ERROR signal

The NPX uses the processor extension request and

acknowledge pins of the M80286 CPU to implement

data transfers with memory under the protection

model of the CPU The full virtual and physical ad-

dress space of the M80286 is available Data for the

M80287 in memory is addressed and represented in

the same manner as for an M8087

The M80287 can operate either directly from the

CPU clock or with a dedicated clock For operation

with the CPU clock (CKM e 0) the M80287 works

at one-third the frequency of the system clock (i e

for an 8 MHz M80286 the 16 MHz system clock is

divided down to 5 3 MHz) The M80287 provides a

capability to internally divide the CPU clock by three

to produce the required internal clock (33% duty cy-

cle) To use a higher performance M80287 (8 MHz)

an M8284A clock driver and appropriate crystal may

be used to directly drive the M80287 with a duty

cycle clock on the CLK input (CKM e 1)

SYSTEM CONFIGURATION WITH

M80386

The M80287 can also be connected as a processor

extension to the M80386 CPU as shown in Figure

4b All software written for M8086 M8087 and

M80286 M80287 is object code compatible with

80386 M80287 and can benefit from the increased

speed of the M80386 CPU

Note that the PEACK input pin is pulled high This is

because the M80287 is not required to keep track of

the number of words transferred during an operand

transfer when it is connected to the M80386 CPU

Unlike the M80286 CPU the M80386 CPU knows

the exact length of the operand being transferred

to from the M80287 After an ESC instruction has

been sent to the M80287 the M80386 processor

extension data channel will initiate the data transfer

as soon as it receives the PEREQ signal from the

M80287 The transfer is automatically terminated by

the M80386 CPU as soon as all the words of the

operand have been transferred

Because of the very high speed local bus of the

M80386 CPU the M80287 cannot reside directly on

the CPU local bus A local bus controller logic is

used to generate the necessary read and write cycle

timing as well as the chip select timings for the

M80287 The M80386 CPU uses I O addresses

800000F8 through 800000FF to communicate with

the M80287 This is beyond the normal I O address

space of the CPU and makes it easier to generate

the chip select signals using A31 and M IO It may

also be noted that the M80386 CPU automatically

generates 16-bit bus cycles whenever it communi-

cates with the M80287

HARDWARE INTERFACE

Communication of instructions and data operands

between the M80286 and M80287 is handled by the

CMD0 CMD1 NPS1 NPS2 NPRD and NPWR sig-

nals I O port addresses 00F8H 00FAH and 00FCH

are used by the M80286 for this communication

When any of these addresses are used the NPS1

input must be LOW and NPS2 input HIGH The

IORC and IOWC outputs of the M82288 identify I O

space transfers (see Figure 4) CMD0 should be

connected to latched M80286 A1 and CMD1 should

be connected to latched M80286 A2

I O ports 00F8H to 00FFH are reserved for the

M80286 M80287 interface To guarantee correct

operation of the M80287 programs must not per-

form any I O operations to these ports

The PEREQ PEACK BUSY and ERROR signals of

the M80287 are connected to the same-named

M80286 input The data pins of the M80287 should

be directly connected to the M80286 data bus Note

that all bus drivers connected to the M80286 local

bus must be inhibited when the M80286 reads from

the M80287 The use of COD INTA and M IO in the

decoder prevents INTA bus cycles from disabling

the data transceivers

The S1 S0 COD INTA READY HLDA and CLK

pins of the M80286 are connected to the same

named pins on the M80287 These signals allow the

M80287 to monitor the execution of ESCAPE in-

structions by the M80826

PROGRAMMING INTERFACE

Table 2 lists the seven data types the M80287 sup-

ports and presents the format for each type These

values are stored in memory with the least signifi-

cant digits at the lowest memory address Programs

retrieve these values by generating the lowest ad-

dress All values should start at even addresses for

maximum system performance

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