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QLX111GRX データシートの表示(PDF) - Intersil

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QLX111GRX
Intersil
Intersil Intersil
QLX111GRX Datasheet PDF : 10 Pages
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QLx111GRx
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR
THE QLx111GRx
Line Silence/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx111GRx contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by
measuring the amplitude of the equalized signal and
comparing that to a threshold set by the voltage at the
DT pin. When the amplitude falls below the threshold,
the output driver stage is muted.
LOS Indicator
Pin LOS is used to output the state of the muting circuitry
to serve as a loss of signal indicator for the device. This
signal is directly derived from the muting signal off the
DT-threshold signal detector output. The LOS signal goes
HIGH when the power signal is below the DT threshold
and LOW when the power goes above the DT threshold.
This feature is meant to be used in optical systems (e.g.
SFP+) where there are no quiescent or electrical-idle
states. In these cases, the DT threshold is used to
determine the sensitivity of the LOS indicator.
Detection Threshold (DT) Pin Functionality
The QLx111GRx is capable of maintaining periods of line
silence by monitoring each channel for loss of signal
(LOS) conditions and subsequently muting the outputs of
a respective channel when such a condition is detected. A
reference voltage applied to the detection threshold (DT)
pin is used to set the LOS threshold of the internal signal
detection circuitry. Voltage control on the DT pin is done
via two external resistors. Both a pull-up and pull-down
resistor are tied to the DT pin, with suggested values
indicated in Figure 8. Other values of the resistors may
also be applicable; therefore customers are advised to
verify DT settings for their specific application.
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx111GRx
7
FN6987.0
October 26, 2009

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