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R8A66170SP データシートの表示(PDF) - Renesas Electronics

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R8A66170SP
Renesas
Renesas Electronics Renesas
R8A66170SP Datasheet PDF : 21 Pages
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R8A66170DD/SP
(b) Internal trigger selected (D1 = 0 in command 1)
In this mode, the trigger signal is generated by the prescaler. Therefore, the cycle time T of output pulse is determined
by the prescaler register value L.
In this case, the oscillator source becomes the PWM counter clock and the output pulse width is determined by the
PWM register value M. (See Fig.6)
Oscillator source
Internal signal
Prescaler output
(Internal trigger)
(at L = 11)
M=0
M=1
PWM output
M=2
M=3
1
f (XIN)
L+1
f (XIN)
"L"
M
f (XIN)
T= L+1
f (XIN)
T :Cycle time (μs)
f(XIN) :Oscillator frequency (MHz)
L :Prescaler set value
M :width set value
Fig.6 (When H width polarity is “H”)
In Mode 1, the retrigger state is caused when the cycle time of trigger pulse gets smaller than the value M of PWM
register.
REJ03F0272-0100 Rev.1.00 Apr.01.2008
Page 8 of 20

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