RA8872L3N データシートの表示（PDF） - RAIO

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RA8872L3N

Character/Graphic TFT LCD Controller

RAIO 

Version 1.1 Brief Specification

RA8872

Character/Graphic TFT LCD Controller

4-4 Clock and Power Interface

Pin Name

XI

XO

RST#

TEST[0:2]

VR1

VR2

ADC_VREF

LDO_VDD

LDO_GND

LDO_OUT

LDO_CAP

CORE_VDD

ADC_VDD

I/O Pin#

Pin Description

Crystal Input Pin

I

28 Input pin for internal crystal circuit. It should be connected to

external crystal to generate the source of PLL circuit. That will

generate the system clock for RA8872.

Crystal Output Pin

O

29 Output pin for internal crystal circuit.

Reset Signal Input

This active-low input performs a hardware reset on the RA8872. It

I

38 is a Schmitt-trigger input for enhanced noise immunity; however,

care should be taken to ensure that it is not triggered if the supply

voltage is lowered.

Test Mode Input

I 40~42 For chip test function, should be connected to GND for normal

operation.

Reference Voltage Input

A 76 This is a reference voltage input. For normal operation, it only need

add a 0.1uF capacitor to ground.

Reference Voltage Output

A 74 This is a reference voltage output. For normal operation, it only

need add a 0.2uF capacitor to ground.

ADC Reference Voltage

A

4 This pin is the reference voltage input of ADC. The reference

voltage could be generated by RA8872 or from external circuit.

P

27, LDO VDD

3.3V power source for LDO. The internal LDO will generate the

79, 1.8V power output.

25, LDO GND

P

78 Ground signal for internal LDO.

LDO Output

P 80 1.8V power generated by internal LDO. It must connect bypass

capacities to prevent power noise.

LDO Capacitor Input

P

30 It must connect 1uF bypass capacities to prevent power noise.

CORE VDD

P

17, Core VDD is 1.8V. The core power input that connects to

57 LDO_OUT. It must connect 1uF bypass capacities to prevent

power noise.

ADC VDD

P

2 ADC 3.3V power signals. Please connect this signal to 3.3V.

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