HN58C65P-25 データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HN58C65P-25

8192-word × 8-bit Electrically Erasable and Programmable CMOS ROM

Hitachi -> Renesas Electronics 

HN58C65 Series

Read Cycle

Parameter

Symbol Min

Max

Unit

Test Conditions

Address to output delay

t ACC

—

250

ns

CE = OE = VIL, WE = VIH

CE to output delay

t CE

—

250

ns

OE = VIL, WE = VIH

OE to output delay

t OE

10

100

ns

CE = VIL, WE = VIH

Address to output hold

t OH

0

—

ns

CE = OE = VIL, WE = VIH

OE, CE high to output float*1

t DF

0

90

ns

CE = VIL, WE = VIH

Note: 1. tDF is defined at which the outputs archieve the open circuit conditions and are no longer driven.

Read Timing Waveform

Address

CE

OE

High

WE

t ACC

tCE

tOE

tOH

tDF

Data Out

Data Out Valid

6

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