NJU6677CL データシートの表示（PDF） - Japan Radio Corporation

部品番号

コンポーネント説明

メーカー

NJU6677CL

88-common x 132-segment BIT MAP LCD DRIVER

Japan Radio Corporation  

NJU6677

No

14

13

Symbol

RD(E)

WR(RW)

I/O

Function

I <In case of 80 Type MPU>

RD signal of 80 type MPU input terminal. Active "L"

During this signal is "L" , D0 to D7 terminals are output.

<In case of 68 Type MPU>

Enable signal of 68 type MPU input terminal. Active "H"

I <In case of 80 Type MPU>

Connect to the 80 type MPU WR signal. Actie "L".

The data on the data bus input syncronizing the rise edge of this signal.

<In case of 68 Type MPU>

The read/write control signal of 68 type MPU input terminal.

R/W

H

L

State

Read

Write

4

SEL68

I MPU interface type selection terminal.

SEL68

H

L

S tate

6 8 Typ e

8 0 Typ e

3

P /S

9,

10

45 to 88

OSC1

OSC2

C0 to

C 43

89 to 220 S0 to

S131

I serial or parallel interface selection terminal.

P/S

Chip Select Data/Command Data

Read/Write serial Clock

"H"

CS

A

D0 to D7 RD,WR

-

"L"

CS

A0

SI(D7) Write Only SCL(D6)

RAM data and status read operation do not work in mode of

the serial interface.

In case of the serial interface (P/S="L"),RD and WR must be fixed

"H" or "L", and D0 to D5 are high impedance.

I System clock input terminal for Maker testing.(This terminal should be Open)

For external clock operation, the clock shoud be input to OSC1 terminal.

O LCD driving signal output terminals.

Segmet output terminals:S 0 to S131

Common output terminals:C 0 to C87

Segment output terminal

The following output voltages are selected by the combination of FR and data

in the RAM.(non of the n-line inverse functions)

O

RAM

Data

FR

Output Voltage

Normal

Reverse

H

VDD

V2

H

L

V5

V3

H

V2

L

L

V3

VDD

V5

264 to

C44 to

221

C 87

Common output terminal

The following output voltages are selected by the combination of FR and status

O of common.

Scan data FR

H

H

L

H

L

L

Output Voltage

V5

VDD

V1

V4

Share Link: