CAT25C03 データシートの表示（PDF） - Catalyst Semiconductor => Onsemi
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CAT25C03 Datasheet PDF : 12 Pages
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CAT25C11/03/05/09/17
DESIGN CONSIDERATIONS
The CAT25C11/03/05/09/17 powers up in a write dis- received, no data will be shifted into the CAT25C11/03/
able state and in a low power standby mode. A WREN 05/09/17, and the serial output pin (SO) will remain in a
instruction must be issued to perform any writes to the high impedance state until the falling edge of CS is
device after power up. Also,on power up CS should be detected again.
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status When powering down, the supply should be taken down
register write the CAT25C11/03/05/09/17 goes into a to 0V, so that the CAT25C11/03/05/09/17 will be reset
write disable mode. CS must be set high after the proper when power is ramped back up. If this is not possible,
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
then, following a brown-out episode, the CAT25C11/
03/05/09/17 can be reset by refreshing the contents of
the Status Register (See Application Note AN10).
rts Figure 7. WRSR Instruction Timing
a CS
P SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
d OPCODE
DATA IN
e SI
0
0
0
0
00
0
1
7
6
5
4
32
10
MSB
u SO
HIGH IMPEDANCE
tin Note: Dashed Line= mode (1, 1) – – – –
n Figure 8. Page Write Instruction Timing
o CS
c0 1 2 3 4 5 6 7 8
21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SK
is OPCODE
BYTE ADDRESS*
DATA IN
DSI
0 0 0 0 X* 0 1 0 AN
A0
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
7..1
0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table.
*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1017, Rev. L
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