MT4LC8M8C2 データシートの表示（PDF） - Micron Technology

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MT4LC8M8C2

8 MEG x 8 EDO DRAM

Micron Technology 

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VCC = +3.3V; f = 1

MHz; TA = 25°C.

3. ICC is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle

wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

7. AC characteristics assume tT = 2.5ns.

8. VIH (MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition

times are measured between VIH and VIL (or

between VIL and VIH).

9. In addition to meeting the transition rate

specification, all input signals must transit

between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

10. If CAS# and RAS# = VIH, data output is High-Z.

11. If CAS# = VIL, data output may contain data from

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

gates and 100pF; and VOL = 0.8V and VOH = 2V.

13. If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous

cycle. To initiate a new cycle and clear the data-

out buffer, CAS# must be pulsed HIGH for tCP.

14. The tRAD (MAX) limit is no longer specified.

tRAD (MAX) was specified as a reference point

only. If tRAD was greater than the specified tRAD

(MAX) limit, then access time was controlled

exclusively by tAA (tRAC and tCAC no longer

applied). With or without the tRAD (MAX) limit,

tAA, tRAC, and tCAC must always be met.

15. The tRCD (MAX) limit is no longer specified.

tRCD (MAX) was specified as a reference point

only. If tRCD was greater than the specified tRCD

(MAX) limit, then access time was controlled

exclusively by tCAC (tRAC [MIN] no longer

applied). With or without the tRCD limit, tAA

and tCAC must always be met.

16. Either tRCH or tRRH must be satisfied for a READ

cycle.

8 MEG x 8

EDO DRAM

17. tOFF (MAX) defines the time at which the output

achieves the open circuit condition and is not

referenced to VOH or VOL.

18.tWCS, tRWD, tAWD, and tCWD are not restrictive

operating parameters. tWCS applies to EARLY

WRITE cycles. If tWCS > tWCS MIN, the cycle is an

EARLY WRITE cycle and the data output will

remain an open circuit throughout the entire

cycle. tRWD, tAWD and tCWD define READ-

MODIFY-WRITE cycles. Meeting these limits

allows for reading and disabling output data and

then applying input data. OE# held HIGH and

WE# taken LOW after CAS# goes LOW results in a

LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,

tCWD and tAWD are not applicable in a LATE

WRITE cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not

possible.

21. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# is LOW and

OE# is HIGH.

22. RAS#-ONLY REFRESH requires that all rows be

refreshed at least once every 64ms (4,096 rows

for the C2 version and 8,192 rows for the P4

version). CBR REFRESH requires that at least

4,096 cycles be completed every 64ms.

23. The DQs open during READ cycles once tOD or

tOFF occur. If CAS# stays LOW while OE# is

brought HIGH, the DQs will open. If OE# is

brought back LOW (CAS# still LOW), the DQs

will provide the previously read data.

24. LATE WRITE and READ-MODIFY-WRITE cycles

must have both tOD and tOEH met (OE# HIGH

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. If OE# is taken back LOW while CAS#

remains LOW, the DQs will remain open.

25. Column address changed once each cycle.

26. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse

width ≤ 10ns, and the pulse width cannot be

greater than one third of the cycle rate. VIL

undershoot: VIL (MIN) = -2V for a pulse width ≤

10ns, and the pulse width cannot be greater than

one third of the cycle rate.

27. NC pins are assumed to be left floating and are

not tested for leakage.

8 Meg x 8 EDO DRAM

D20_2.p65 – Rev. 5/00

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000, Micron Technology, Inc.

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