SZM-2166Z-EVB1 データシートの表示（PDF） - Sirenza Microdevices => RFMD
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SZM-2166Z-EVB1 Datasheet PDF : 16 Pages
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Pin Out Description
Pin #
Function
7, 11,12, 22, 29, 31,
39, 40
NC
1,10, 21, 30
GND
2
VC1
3
VBIAS12
4-5
R1A-R2A
6
RFIN
8
VPC1
9
VPC2
13, 38
14-15
17-18
33-34
36-37
16,35
19
20
23-28
32
VC2A, VC2B
C1A-C2A
C3A-C4A
C4B-C3B
C2B-C1B
VB3A, VB3B
VPC3
VDET
RFOUT
VBIAS3
Preliminary
SZM-2166Z 2.3-2.7GHz 2W Power Amp
Description
These are no connect (NC) pins and are not wired inside the package. It is recommended to con-
nect them as shown in the application circuit to achieve the stated performance.
These pins are internally grounded inside the package to the backside ground paddle. It is recom-
mended to also ground them external to the package to achieve the specified performance.
This is the collector of the first stage.
This is the supply voltage for the active bias circuit of the 1st and 2nd stages.
A resistor is tied across these pins internal to the package.
This is the RF input pin. It is DC grounded inside the package. Do not apply DC voltage to this pin.
Power up/down control pin for the 1st stage. An external series resistor is required for proper set-
ting of bias levels depending on control voltage. The voltage on this pin should never exceed the
voltage on pin 3 by more than 0.5V unless the supply current from pin 3 is limited < 10mA.
Power up/down control pin for the 2nd stage. Power down VPC<1V for step attenuator function
enable. An external series resistor is required for proper setting of bias levels depending on control
voltage. The voltage on this pin should never exceed the voltage on pin 3 by more than 0.5V unless
the supply current from pin 3 is limited < 10mA.
These two pins are connected internal to the package and connect to the 2nd stage collector. To
achieve specified performance, the layout of these pins should match the Recommended Land
Pattern, pg. 13.
These pins have capacitors across them internal to the package as shown in the below schematic.
They are used as tuning and RF coupling elements between the 2nd and 3rd stage.
These are the connections to the base of the 3rd stage output device. To achieve specified perfor-
mance, the layout of these pins should match the Recommended Land Pattern, pg. 13.
Power up/down control pin for the 2nd stage. An external series resistor is required for proper set-
ting of bias levels depending on control voltage. The voltage on this pin should never exceed the
voltage on pin 32 by more than 0.5V unless the supply current from pin 33 is limited < 10mA.
This is the output port for the power detector. It samples the power at the input of the 3rd stage.
These are the RF output pins and DC connections to the 3rd stage collector.
This is the supply voltage for the active bias circuit of the 3rd stage.
Simplified Device Schematic
GND
40
1
VC1
VBIAS12
R1A
R2A
RFIN
NC
VPC1
VPC2
GND 10
11
31
30 GND
NC
RFOUT
RFOUT
RFOUT
RFOUT
RFOUT
RFOUT
NC
21
20
GND
303 South Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-105683 Rev B
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