S24C01A データシートの表示（PDF） - Seiko Instruments Inc
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S24C01A Datasheet PDF : 23 Pages
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CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
S
W
T
R
A
I
R
DEVICE
T
T
ADDRES
E WORD ADDRESS (n)
DATA (n)
DATA (n+1)
SDA LINE
1 0 1 0 A2 A1A0 0 W7W6W5W4W3W2W1W0 D7 D6 D5 D4 D3 D2 D1 D0 D7
D0 D7
M
LRA
A
S
S/C
C
B
BWK
K
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
A
C
K
ADR INC
A
C
K
ADR INC
S
T
O
DATA (n+x)
P
D0
A
C
K
ADR INC
Figure 11 Page Write
In the S-24C01A or S-24C02A, the lower 3 bits of the word address are automatically incremented
each when the EEPROM receives 8-bit write data.
Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the
lower 3 bits are rolled over and overwritten.
In the S-24C04A, the lower 4 bits at the word address are automatically incremented each when the
EEPROM receives 8 bit write data.
Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address
P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.
6.3 Acknowledgment Polling
Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.
After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are
prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device.
Accordingly, the master device transmits the start condition signal and the device address read/write
instruction code to the EEPROM (namely, the slave device) to detect the response of the slave
device. This allows users to know when the rewriting of the EEPROM is finished.
That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is
rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting
has been completed. It is recommended to use read instruction "1" for the read/write instruction
code transmitted by the master device.
6.4 Write Protection
The S-24C02A and the S-24C04A are capable of protecting the memory. When the WP pin is
connected to VCC, writing to 50% of the latter half of all memory area (080h to 0FFh in the S-24C02A;
100h to 1FFh in the S-24C04A) is prohibited. Even when writing is prohibited, since the controller
inside the IC is operating, the response to the signal transmitted by the master device is not available
during the time of writing (tWR).
When the WP pin is connected to GND, the write protection becomes invalid, and writing in all
memory area becomes available. However, when there is no need for using write protection, always
connect the WP pin to GND.
10
Seiko Instruments Inc.
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