LF43891 データシートの表示（PDF） - LOGIC Devices

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LF43891

9 x 9-bit Digital Filter

LOGIC Devices 

DEVICES INCORPORATED

LF43891

9 x 9-bit Digital Filter

Controls

DCM1-0 — Decimation Control

SENBH — MSB Output Enable

DIENB — Data Input Enable

The DIENB input enables the X

register of every filter cell. While

DIENB is LOW, the X registers are

loaded with the data present at the

DIN8-0 inputs on the rising edge of

CLK. While DIENB is HIGH, all bits

of DIN8-0 are forced to zero and a

rising edge of CLK will load the X

register of every filter cell with all

zeros. DIENB must be low one clock

cycle prior to presenting the input

data on the DIN8-0 input since it is

latched and delayed internally.

CIENB — Coefficient Input Enable

The CIENB input enables the C and D

registers of every filter cell. While

CIENB is LOW, the C and appropriate

D registers are loaded with the

coefficient data on the rising edge of

CLK. While CIENB is HIGH, the

contents of the C and D registers are

held and the CLK signal is ignored.

By using CIENB in its active state,

coefficient data can be shifted from

cell to cell. CIENB must be low one

clock cycle prior to presenting the

coefficient data on the CIN8-0 input

since it is latched and delayed inter-

nally.

COENB — Coefficient Output Enable

The COENB input enables the

COUT8-0 output. When COENB is

LOW, the outputs are enabled. When

COENB is HIGH, the outputs are

placed in a high-impedance state.

The DCM1-0 inputs select the num-

ber of decimation registers to use

(Table 1). Coefficients are passed

from one cell to another at a rate

determined by DCM1-0. When no

decimation registers are selected,

the coefficients are passed from cell

to cell on every rising edge of CLK

(no decimation). When one decima-

tion register is selected, the coeffi-

cients are passed from cell to cell on

every other rising edge of CLK (2:1

decimation). When two decimation

registers are selected, the coeffi-

cients are passed from cell to cell on

every third rising edge of CLK (3:1

decimation) and so on. DCM1-0 is

latched and delayed internally.

ADR2-0 — Cell Accumulator Select

The ADR2-0 inputs select which cell’s

accumulator will available at the

SUM25-0 output or added to the

output stage accumulator. In both

cases, ADR2-0 is latched and delayed

by one clock cycle. If the same

address remains on the ADR2-0 inputs

for more than one clock cycle,

SUM25-0 will not change if the con-

tents of the accumulator changes.

Only the result from the first selection

of the cell (first clock cycle) by ADR2-0

will be available. ADR2-0 is also used

to select which accumulator to clear

when ERASE is LOW.

When SENBH is LOW, SUM25-16 is

enabled. When SENBH is HIGH,

SUM25-16 is placed in a high-imped-

ance state.

SENBL — LSB Output Enable

When SENBL is LOW, SUM15-0 is

enabled. When SENBL is HIGH,

SUM15-0 is placed in a high-imped-

ance state.

RESET — Register Reset Control

When RESET is LOW, all registers are

cleared simultaneously except the cell

accumulators. RESET can be used

with ERASE to clear all cell accumula-

tors. RESET is latched and delayed

internally. Refer to Table 2.

ERASE — Accumulator Erase Control

When ERASE is LOW, the cell accu-

mulator specified by ADR2-0 is

cleared. When RESET is LOW in

conjunction with ERASE, all cell

accumulators are cleared. Refer to

Table 2.

Video Imaging Products

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08/16/2000–LDS.43891-J

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