74LVC823ADB データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

74LVC823ADB

9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)

Philips Electronics 

Philips Semiconductors

9-bit D-type flip-flop with 5-volt tolerant

inputs/outputs; positive-edge trigger (3-State)

Product specification

74LVC823A

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 2.7V to 3.6V

• Complies with JEDEC standard no. 8-1A

• Inputs accept voltages up to 5.5V

• CMOS low power consumption

• Direct interface with TTL levels

• 9-bit positive edge-triggered register

• Independent register and 3-State buffer operation

• Flow-through pin-out architecture

DESCRIPTION

The 74LVC823A is a high performance, low-power, low-voltage

Si-gate CMOS device and superior to most advanced CMOS

compatible TTL families.

Inputs can be driven from either 3.3V or 5.0V devices. In 3-state

operation, outputs can handle 5V. This feature allows the use of

these devices as translators in a mixed 3.3V/5V environment.

The 74LVC823A is a 9-bit D-type flip-flop with common clock (CP),

Clock Enable (CE), Master Reset (MR) and 3-State outputs for

bus-oriented applications.

The nine flip-flops will store the state of their individual D-inputs that

meet the set-up and hold times requirements on the LOW-to-HIGH

CP transition provided CE is LOW. When CE is HIGH the flip-flops

hold their data.

A LOW on MR resets all flip-flops.

When OE is LOW, the contents of the nine flip-flops is available at

the outputs. When OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the

state of the flip-flops.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

CP to Qn

Propagation delay

MR to Qn

CL = 50 pF;

VCC = 3.3 V

fmax

Maximum clock frequency

CL = 50 pF;

VCC = 3.3 V

CI

Input capacitance

CPD

Power dissipation capacitance per

flip-flop

Notes 1 and 2

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC

TYPICAL

5.1

5.2

150

5.0

27

ORDERING INFORMATION

PACKAGES

24-Pin Plastic SO

24-Pin Plastic SSOP Type II

24-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

ORDERING CODE

74LVC823A D

74LVC823A DB

74LVC823A PW

UNIT

ns

ns

MHz

pF

pF

PKG. DWG. #

SOT137-1

SOT340-1

SOT355-1

1998 Sep 24

2

853-2124 20078

Share Link: