SAA7219/HS/C2 データシートの表示（PDF） - Philips Electronics

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SAA7219/HS/C2

MPEG2 Transport RISC processor

Philips Electronics 

SYMBOL

PIN

JTAG and Test interface (5 pins)

TDO

178

I/O

BUFFER TYPE

O 3-state, 2 mA output drive

TDI

179

I TTL input

TMS

180

I TTL input

TRST

181

I TTL input

TCK

184

I TTL input

EJTAG extension reserved for PR3930 (4 pins)

DSU_CLK

185

O 2 mA output drive

PCST0 to PCST2

186, 188, 189

O 2 mA output drive

VOLT(1)

DESCRIPTION

3.3 V

5V

5V

5V

5V

Test data output/Target PC output.

Real-Time Trace mode off. Serial output data is

shifted from JTAG instruction register to the TDO

pin at the falling of the TCK clock. When no data is

shifted out, TDO is 3-stated.

Real-Time Trace mode on. TDO provides

non-sequential program counter output at the

processor clock speed.

Test data input/Debug interrupt.

Real-Time Trace mode off. Serial input data (TDI) is

shifted into the JTAG instruction register or data

register on the rising edge of the TCK clock,

depending of the TAP controller state.

Real-Time Trace mode on. An active LOW level at

this input sampled by TCK positive edge, is used as

interrupt to switch the Real-Time Trace mode off

(standard JTAG).

Test mode select. This input is decoded by the TAP

controller to control test operation. Sampled on

TCK rising edge.

Test reset. Active LOW level for asynchronous reset

of the EJTAG module, independent of the processor

logic.

Test clock. Input clock used to shift data into or out

the JTAG instruction or data register.

3.3 V

3.3 V

DSU clock is equivalent to the processor clock.

Captures address and data from pin TDO when PC

trace mode is on. Is 3-stated when bit 0 or 15 of the

JTAG Control Register is logic 0.

CPU status: debug mode, pipeline stall, occurrence

of exception

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