SAA7219/HS/C2 データシートの表示（PDF） - Philips Electronics

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SAA7219/HS/C2

MPEG2 Transport RISC processor

Philips Electronics 

Philips Semiconductors

MPEG2 Transport RISC processor

Preliminary specification

SAA7219

1 FEATURES

• Conditional access descrambling Digital Video

Broadcasting (DVB) compliant and MULTI2 compliant

• Stream demultiplexing: Transport Stream (TS),

Packetized Elementary Stream (PES), program and

proprietary streams

• Internal 32-bit MIPS RISC based Central Processing

Unit (CPU) supporting MIPS16 instruction set and

running at 81 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool

support

• Package: SQFP208.

1.1 External interfaces

• Versatile compressed stream input at 108 Mbits/s

• A 32-bit microcontroller extension bus supporting

DRAM, SDRAM, Flash, (E)PROM and external memory

mapped I/O devices. It also supports a synchronous

interface to communicate with the integrated MPEG

Audio Video Graphics Decoder (AVGD) SAA7215 at

40.5 Mbytes.

• An IEEE 1284 interface (Centronics) supporting master

and slave modes. Usable as a general purpose port.

• An interface to IEEE 1394 devices (such as Philips

PDI 1394 chip-set)

• Two UART (RS232) data ports with Direct Memory

Access (DMA) capabilities (187.5 kbits/s) including

hardware flow control signals RXD, TXD, RTS and CTS

for modem support

• A Synchronous Serial Interface (SSI) to connect an

off-chip modem analog front-end

• An elementary UART with DMA capabilities, dedicated

to front panel devices for instance

• Two dedicated smart-card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers with DMA

capabilities, supporting the standard (100 kbit/s) and

fast (400 kbits/s) I2C-bus modes

• 32 general purpose, bidirectional I/O interface pins, 8 of

which may also be used as interrupt inputs

• One Pulse Width Modulated (PWM) output with 8-bit

resolution

• A General Purpose/High Speed (GP/HS) interface

supporting stream recording through IEEE 1394

interface IC

• An extended JTAG interface for board test support.

1.2 CPU related features

The SAA7219 contains an embedded RISC CPU, which

incorporates the following features:

• A 32-bit PR3930 core running at 81 MHz

• 8-kbyte, 2-way set associative instruction cache

• 4-kbyte, 4-way set associative data cache

• A programmable Low-power mode, including wake-up

on interrupt

• A memory management unit with 32 odd/even entries

and variable page sizes

• Multiply/accumulate/divide unit with fast

multiply/accumulate for 16-bit and 32-bit operands

• Two fully independent 24-bit timers and one 24-bit timer

including watchdog facilities

• A real-time clock unit (active in Sleep mode)

• Built-in software debug support unit as part of Extended

Enhanced JTAG debug interface

• On-chip SRAM of 4 kbytes for storing code which needs

fast execution.

1.3 MPEG-2 systems features

• Hardware based parsing of Transport Stream (TS),

Philips Semiconductors program and proprietary

software data streams. Maximum input rate is

108 Mbits/s.

• A real-time descrambler consisting of 3 modules:

– A control word bank containing 14 pairs (odd, even)

of control words and a default control word

– The DVB descrambler core implementing the stream

decipher and block decipher algorithms

– The MULTI2 descrambler algorithm implementing

the CBC and OFB mode descrambling functions.

1999 Sep 20

3

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