SAA7219/HS/C2 データシートの表示（PDF） - Philips Electronics

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SAA7219/HS/C2

MPEG2 Transport RISC processor

Philips Electronics 

Philips Semiconductors

MPEG2 Transport RISC processor

Preliminary specification

SAA7219

• Hardware section filtering based on 32 different Packet

Identifiers (PIDs) with a flexible number of filter

conditions (8 or 4-byte condition plus 8 or 4-byte mask)

per PID and a total filter capacity of 40 (8-byte condition

checks) or up to 80 (4-byte condition checks) filter

conditions:

– 4 TS/PES filters for retrieval for data at TS or PES

level for applications such as subtitling, TXT or

retrieval of private data

– Flexible DMA based storage of the 32 section

substreams and 4 TS/PES data substreams in the

external memory

• System time base management with a double counter

mechanism for clock control and discontinuity handling,

2 Presentation Time Stamp (PTS)/Decoding Time

Stamp (DTS) timers

• A GP/HS filter which can serve as an alternate input

from for example IEEE 1394 devices. The IEEE 1394

GP/HS mode supports packet insertion and has an

internal SRAM for storing 2 packets. It can also output

either scrambled or descrambled TS to IEEE 1394

devices.

2 GENERAL DESCRIPTION

2.1 SAA7219 overview

The device is part of a comprehensive source decoding kit

which contains all the hardware and software required to

receive and decode MPEG-2 transport streams, including

descrambling, demultiplexing. In addition, it includes a

PR3930 core which is a 32-bit MIPS RISC-based CPU

core supporting the MIPS 16 instruction set to reduce

memory requirements and several peripheral interfaces

such as UARTs, I2C-bus units, an IEC 1883, and an

IEEE 1284 (Centronics) interface. The SAA7219 is

therefore capable of performing all controller tasks in

digital television receiver applications such as set-top

boxes. Furthermore, the SAA7219 is compliant to DVB

and MULTI2 standards.

The SAA7219 receives transport streams through a

versatile stream input interface capable of handling both

byte-parallel and bit-serial streams in various formats,

supporting data streams up to and including 13.5 Mbyte/s

(108 Mbits/s). The stream data is first applied to an on-chip

descrambler incorporating a DVB descrambling algorithm,

on the basis of 14 control word pairs stored in on-chip

RAM. Demultiplexing is subsequently applied to the

stream, to separate up to 32 individual data streams.

The demultiplexer section includes clock recovery and

timebase management. Program Specific Information

(PSI), Service Information (SI), Conditional Access (CA)

messages and private data are selected and stored in

external memory, for subsequent off-line processing by

the internal PR3930 CPU core.

To support advanced board testing facilities the SAA7219

includes boundary scan test hardware, according to the

EJTAG standard. The device features a Low-power sleep

mode, which is capable of sustaining set-top box stand-by

functionality, thus eliminating the need for a separate

front-panel controller. The SAA7219 requires a supply

voltage of 3.3 V and most devices input and output

interfaces are 5 V tolerant except the extension bus which

is 3.3 V only. The SAA7219 is mounted in a SQFP208

package.

2.2 SAA7219 in a DVB system

The SAA7219 has been designed to offer optimum

performance when used with the SAA7215 for MPEG-2e

AVG decoding.

• Synchronous bus interface transfer at 40.5 MHz on

16 bits

• SAA7215 has one dedicated SDRAM for MPEG-2e

audio video handling and one for graphics and CPU

data. The second memory offers high bandwidth and

low latency to the SAA7219 when accessing it to

download graphics or executing some applications. This

enables a high level of performance together with a low

system cost by having one SDRAM for graphics and

CPU data.

3 ORDERING INFORMATION

TYPE NUMBER

NAME

PACKAGE

DESCRIPTION

SAA7219HS SQFP208 plastic shrink quad flat package; 208 leads (lead length 1.3 mm);

body 28 × 28 × 3.4 mm

VERSION

SOT316-1

1999 Sep 20

4

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