SAA7740 データシートの表示（PDF） - Philips Electronics

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SAA7740

Digital Audio Processing IC (DAPIC)

Philips Electronics 

Philips Semiconductors

Digital Audio Processing IC (DAPIC)

Product specification

SAA7740H

PINNING

SYMBOL PIN

DESCRIPTION

RST

SCL

SDA

1 reset input (active LOW)

2 serial clock input (I2C-bus)

3 serial data input/output (I2C-bus)

MUTE

4 mute input (active HIGH)

n.c.

5 not connected

n.c.

6 not connected

VDD

VDD

VSS

CAS

7 supply voltage

8 supply voltage

9 ground supply

10 column address strobe (DRAM)

(active LOW)

D0

11 input/output data bus line 0 (DRAM)

D1

12 input/output data bus line 1 (DRAM)

VSS

13 ground supply

OE

14 output buffer enable (DRAM)

(active LOW)

D2

15 input/output data bus line 2 (DRAM)

D3

16 input/output data bus line 3 (DRAM)

CAS2

17 second column address strobe

(active LOW)

WE

18 write enable (DRAM; active LOW)

RAS

19 row address strobe (DRAM;

active LOW)

A8B

20 inverse MSB address line output

(DRAM)

A8

21 address line output 8 (DRAM)

A7

22 address line output 7 (DRAM)

A6

23 address line output 6 (DRAM)

A5

24 address line output 5 (DRAM)

VSS

25 ground supply

VDD

26 supply voltage

A4

27 address line output 4 (DRAM)

A3

28 address line output 3 (DRAM)

A2

29 address line output 2 (DRAM)

A1

30 address line output 1 (DRAM)

A0

31 address line output 0 (DRAM)

VDD

MUX

32 supply voltage

33 address latch strobe output (SRAM)

SYMBOL PIN

DESCRIPTION

DO1D

34 digital audio output 1 (I2S-bus)

DO2D

35 digital audio output 2 (I2S-bus)

DOWS

36 digital audio input word select

DOBCK 37 digital audio input serial bit clock

VDD

38 supply voltage

n.c.

39 not connected

VSS

DI1D

40 ground supply

41 digital audio input 1 (I2S-bus)

DI2D

42 digital audio input 2 (I2S-bus)

DIWS

43 digital audio input word select

DIBCK

44 digital audio input serial bit clock

TSTCLK

45 clock input for test mode

(should be tied LOW)

VSS

TST1

46 ground supply

47 test pin input 1

(should be tied LOW)

TST2

48 test pin input 2

(should be tied LOW)

TST3

49 test pin input 3

(should be tied LOW)

VSS

50 ground supply

AS1

51 address select input 1 (I2C-bus)

AS2

52 address select input 2 (I2C-bus)

VDD

VDD

VSS

CLK1/

XTAL1

53 supply voltage

54 supply voltage

55 ground supply

56 clock or crystal input

n.c.

57 not connected

n.c.

58 not connected

XTAL2

59 crystal output 2

VDDX

VSSX

SCCLK

60 crystal supply voltage

61 crystal ground supply

62 scan test clock input

(should be tied LOW)

CLKO

63 clock signal output

ALL

64 mode select input

(should be tied HIGH)

1997 May 30

4

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