SAB80C166 データシートの表示（PDF） - Siemens AG
部品番号
コンポーネント説明
メーカー
SAB80C166 Datasheet PDF : 52 Pages
| |||
SAB 80C166/83C166
Pin Definitions and Functions (cont’d)
Symbol
NMI
ALE
RD
P1.0 –
P1.15
P5.0 –
P5.9
P2.0 –
P2.15
Pin
Input
Number Output
29
I
25
O
26
O
30-37 I/O
40-47
48-53 I
56-59 I
62-77 I/O
62
I/O
75
I/O
O
76
I/O
O
77
I/O
I
Function
Non-Maskable Interrupt Input. A high to low transition at this pin
causes the CPU to vector to the NMI trap routine. When the
PWRDN (power down) instruction is executed, pin NMI must be
low in order to force the SAB 80C166 to go into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pull NMI high externally.
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
Port 1 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state. Port 1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode.
Port 5 is a 10-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 10)
analog input channels for the A/D converter, where P5.x equals
ANx (Analog input channel x).
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state.
The following Port 2 pins also serve for alternate functions:
P2.0
CC0IO CAPCOM: CC0 Cap.-In/Comp.Out
...
...
...
P2.13 CC13IO CAPCOM: CC13 Cap.-In/Comp.Out,
BREQ External Bus Request Output
P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out,
HLDA External Bus Hold Acknowl. Output
P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,
HOLD External Bus Hold Request Input
Semiconductor Group
5
Share Link: 