XC226X データシートの表示（PDF） - Infineon Technologies

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XC226X

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Infineon Technologies 

XC2267 / XC2264

XC2000 Family Derivatives

Preliminary

Functional Description

3

Functional Description

The architecture of the XC226x combines advantages of RISC, CISC, and DSP

processors with an advanced peripheral subsystem in a very well-balanced way. In

addition, the on-chip memory blocks allow the design of compact systems-on-silicon with

maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data

SRAM) and the set of generic peripherals are connected to the CPU via separate buses.

Another bus, the LXBus, connects additional on-chip resources as well as external

resources (see Figure 3). This bus structure enhances the overall system performance

by enabling the concurrent operation of several subsystems of the XC226x.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the XC226x.

PSR A M

16/32/64 Kbytes

Program Flash 0

256 Kbytes

Program Flash 1

192/256 Kbytes

Program Flash 2

0/64/256 Kbytes

D PR A M

2 Kbytes

D SR A M

16 Kbytes

CPU

C166SV2 - Core

Oscillators/PLL, System Fct.

Clock, Reset, Power Control,

Stand-By RAM

Interrupt & PEC

Interrupt Bus

OCDS

Debug Support

EB C

LXBus Control

External Bus

C o n tro l

WDT

RTC

ADC1 ADC0

8-Bit/ 8-Bit/

10-Bit 10-Bit

8 Ch. 16 Ch.

GPT

T2

T3

T4

... CC2 CCU63 CCU60

T7 T12

T12

T8 T13

T13

T5

BRTG6en

USIC2 USIC1 USIC0

2 Ch., 2 Ch., 2 Ch.,

64 x 64 x 64 x

Buffer Buffer Buffer

M ulti

CAN

RS232, RS232, RS232,

LIN, LIN, LIN,

SPI, SPI, SPI,

IIC, IIS IIC, IIS IIC, IIS

5 ch.

P1 5

Port 5

5

11

P1 0

16

P7 P6 P4

53 4

P2

P1 P0

13

8

8

Figure 3 Block Diagram

MC_XC226X_BLOCKDIAGRAM

Data Sheet

28

V0.1, 2007-02

Draft Version

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