XC2000 データシートの表示（PDF） - Infineon Technologies

部品番号

コンポーネント説明

メーカー

XC2000

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Infineon Technologies 

XC2267 / XC2264

XC2000 Family Derivatives

Preliminary

Electrical Parameters

Bus Cycle Control via READY Input

The duration of an external bus cycle can be controlled by the external circuitry via the

READY input signal. The polarity of this input signal can be selected.

Synchronous READY permits the shortest possible bus cycle but requires the input

signal to be synchronous to the reference signal CLKOUT.

Asynchronous READY puts no timing constraints on the input signal but incurs one

waitstate minimum due to the additional synchronization stage. The minimum duration

of an asynchronous READY signal to be safely synchronized must be one CLKOUT

period plus the input setup time.

An active READY signal can be deactivated in response to the trailing (rising) edge of

the corresponding command (RD or WR).

If the next following bus cycle is READY-controlled, an active READY signal must be

disabled before the first valid sample point for the next bus cycle. This sample point

depends on the programmed phases of the next following cycle.

Data Sheet

93

V0.1, 2007-02

Draft Version

Share Link: