SC1403ITSTR データシートの表示（PDF） - Semtech Corporation
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SC1403ITSTR Datasheet PDF : 31 Pages
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SC1403
POWER MANAGEMENT
Functional Information (Cont.)
PRELIMINARY
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Resistance
(ohm)
Vref
Deviation
511
2.67K 49.9K 255K 1Meg
8.3mV 3.1mV 0.5mV 0.3mV 0mV
Current Sense (CSH, CSL)
SHDN ON3 ON5 MODE DESCRIPTION
Low
X
X
Shut-
Minimum bias
down
current
High Low Low Standby VREF and VL
regulator
enable
Output current of each supply is sensed as the voltage between
the CSH and CSL pins. Overcurrent is detected when the current
sense voltage exceeds +55/-50 mV typical. A positive overcurrent
turns off the high-side driver, a negative overcurrent turns off the
low-side driver; each on a cycle-by-cycle basis. Output current can
be sensed by DCR (lossless) sensing, or optionally with a current-
sense resistor; see Applications Information.
Oscillator
When the SYNC pin is high the oscillator runs at 300kHz; when
SYNC is low the frequency is 200kHz. The oscillator can be
synchronized to the falling edge of a clock on the SYNC pin with a
frequency between 240kHz and 350kHz. In general, 200kHz
operation provides highest efficiency, while 300kHz is used to
obtain smaller output ripple and/or smaller filter components.
High High High
Run
Mode
Both SMPS
Running
Output Voltage Selection
If FBx is grounded, internal resistors determine 3.3V and/or 5V
output voltages. In adjustable mode, the internal resistors are
disabled and the output is determined by external resistors, based
on 2.5V regulated at the FB pin. The output voltage is determined
according the following formula. Rdown should not exceed 10
Kohms.
3V or 5V
FB3 or FB5
Rup
Rdown
Fault Protection
In addition to cycle-by-cycle current limit, the SC1403 provides
overtemperature, output overvoltage, and undervoltage
protection. Overtemperature protection will shut the device down
if die temperature exceeds 150°C, with 10°C hysteresis.
If either SMPS output is more than 10% above its nominal value,
both SMPS are latched off and the low side mosfets are latched
on. To prevent the output from ringing below ground in a fault
condition, a 1A Schottky diode should be placed across each output.
Two different levels of undervoltage (UV) are detected. If the output
falls 9% below its nominal value, the RESET# output is pulled low.
If the output falls 25% below its nominal value, both SMPS are
latched off.
Both of the latched faults (OVP and UV) persist until SHDN or ON3
is toggled, or the V+ input is brought below 1V.
Shutdown and Operating Modes
Holding the SHDN pin low disables the SC1403, reducing the V+
input current to less than 10uA. When SHDN is high, the part
enters standby mode where the VL regulator and VREF are enabled.
Turning on either SMPS will put the SC1403 in run mode.
Vout
=
2 . 5 ⋅ 1 +
Rup
Rdown
Power up Controls and Soft Start
The user controls the SC1403 RESET# through the SEQ, ON3 and
ON5 pins, as shown in the Startup Sequence Chart. At startup,
RESET# is held low for 32K switching cycles, and then RESET# is
determined by the output voltages and the SEQ pin.
To prevent surge currents at startup, each SMPS has a counter
and DAC to incrementally raise the current limit (CSH-CSL voltage).
The current limit follows discrete steps of typically 25%, 40%, 60%,
80%, and 100%, each step lasting 128 clock cycles. To charge up
the output capacitors, inductor current at startup must exceed
load current. When the output voltage reaches it’s nominal value
the SMPS will reduce duty cycle, but the excess LI2 energy of the
inductor must flow into the load and output capacitors. If the
output capacitor is relatively small, the peak output voltage can
approach the overvoltage trip point. To prevent nuisance OVP at
startup, the inductance and capacitance must meet the following
criteria:
L MAX
C MIN
≤
V O _ NOM 2
IL MAX _ OC 2
⋅ 1 .59
ILMAX_OC is the maximum inductor current set by the current-limit
components, and VO_NOM is the nominal output voltage.
2004 Semtech Corp.
10
United States Patent No. 6,377,032
www.semtech.com
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