SC1544 データシートの表示（PDF） - Semtech Corporation
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SC1544 Datasheet PDF : 15 Pages
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SC1544
POWER MANAGEMENT
Power Matrix
This table shows which output is powered from which supply under each system state.
PRELIMINARY
System USB PCI /S3 /S5 PWR_OK 3.3V/2.5V Dual 3.3V 5V 3.3V/1.5V 1.8V(2)
State
Memory
Dual Dual AGP(2)
Comments
S0
X(1) X(1)
1
1
1
3.3V
3.3V 5V
3.3V 3.3V
S3
X(1) X(1) 0
1
0
5VSB
5VSB 5VSB ON
ON
S5
0 000
0
OFF
OFF OFF
ON
ON All outputs off
0 100
0
OFF
5VSB OFF
ON
ON
PCI enabled
1 000
0
OFF
OFF 5VSB ON
ON USB enabled
1 100
0
OFF
5VSB 5VSB ON
ON
PCI & USB
enabled
Notes:
(1) X = dont care. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and
USB pins. These outputs are only controlled by the sate of the PCI and USB pins in S5.
(2) Gate 7 and Gate 8 are high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown
in the table, the AGP and 1.8V outputs are only present in S0, and will ramp with the 3.3V supply as it comes up.
This avoids dips in the 3.3V supply which would otherwise occur if Gate 7 and Gate 8 went high after the 3.3V
supply came up, demanding high currents to charge output capacitors. If powered from 5VSB they can be used to
create 1.5VSB, 1.8VSB or 3.3VSB as required.
Gates At A Glance
This table shows which gate drive pin controls which MOS.ET:
Gate Number: Pin Number:
Drives the FET between:
FET mode:
1
18
5VSB
5V Dual
pass device
2
19(1)
5V
5V Dual
pass device
3
19(1)
3.3V
3.3V Dual
pass device
4
22
5VSB
3.3V Dual
linear regulator
and
5
1
3.3V
3.3V/2.5V Dual Memory pass device/linear regulator(2)
6
3
5VSB
3.3V/2.5V Dual Memory
linear regulator
7
4
3.3V
AGP
linear regulator
8
24
3.3V
1.8V
linear regulator
Notes:
(1) Note common pin for Gate 2 and Gate 3 - both .ETs are operating as pass devices only in S0.
(2) .ET is acting as a pass device for 3.3V Dual Memory and as a linear regulator for 2.5V Dual Memory.
2002 Semtech Corp.
8
www.semtech.com
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