SC4611 データシートの表示（PDF） - Semtech Corporation
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SC4611 Datasheet PDF : 11 Pages
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SC4611
POWER MANAGEMENT
Applications Information (Cont.)
OVERCURRENT PROTECTION
POWER OK MONITOR
SC4611 includes a precision current sense comparator for
maximum flexibility. The current feedback can be taken
either from the output inductor for lossless sensing and
better efficiency, or from a series resistor for improved
accuracy. An offset current of 1.225/RT pulls up on the CS-
pin, providing an offset voltage across a resistance on the
input to this pin. The offset voltage should be set to > 50
mV. A voltage across the current sense resistor of greater
than this value will produce a current limit pulse. There is
30% hysteresis on the offset current. Since the offset
current into CS- is set by RT, the current limit needs to be
adjusted if the frequency setting is changed. Note that the
operational limit for CS- and CS+ inputs is 0.5V below the
AVCC supply.
The first stage of protection against overloads is peak
current limiting on a pulse by pulse basis. Once an overload
is sensed, the high side FET is turned off and held low for
the rest of the cycle. This provides peak current limiting on
a pulse by pulse basis. The final response of the device to
a severe overload can be programmed using the CLM pin.
If the CLM pin is connected to AVCC, the hiccup mode is
enabled. A soft-start/hiccup cycle is initiated if 64 current
limit pulses are detected in any counting period of 128
oscillator cycles. The SS capacitor is discharged with a 0.6
mA sink current. There will be 3 dummy soft-starts, i.e. the
SS pin will be pulled up to 2V and then discharged to < 1V.
This will be repeated 7 times, and if the overload persists
the part will be latched off on the eighth attempt. Reset is
by recycling the input power. During the hiccups, the device
will operate in asynchronous mode, just as in the power-
up sequence.
In some cases the repeated soft start cycling may not be
desirable, depending on the nature of load. If the CLM is
taken low to AGND, the hiccup mode will be skipped. When
an overcurrent event occurs a comparator detects it and
puts out a signal into a latch counter. The counter keeps
track of the number of current-limit pulses and is reset
after every 128 oscillator cycles. If 64 current-limit pulses
are detected in any counting period of 128 cycles, the SS
pin will be pulled low. The device is latched off until power
is recycled. The CLM pin should be connected to either
AGND or AVCC at all times and should not be left open.
The power OK circuitry monitors the FB input of the error
amplifier. If the voltage on this input goes above 0.55V or
below 0.45V the POK pin is pulled low. The POK is an open
drain output and is held low until the end of the startup
sequence i.e. till the SS pin reaches 2V or more.
OVERVOLTAGE AND THERMAL PROTECTION
The overvoltage input can be connected to OVP pin with a
low reference of 0.5V. If this feedback exceeds the
reference the low side FET is continuously gated on to
crowbar the input VIN. This feature may be used to protect
the load from possible overvoltage in case the high side
FET fails and shorts. The crowbar current in the power
devices is limited only by the source of VIN.
SC4611 also incorporates thermal protection. If the chip
temperature exceeds approximately 150 Deg C, the outputs
are shutdown.
ERROR AMPLIFIER DESIGN
SC4611 is a voltage mode buck controller that utilizes an
externally compensated high bandwidth error amplifier to
regulate output voltage. The power stage of the
synchronous rectified buck converter control-to-output
transfer function is as shown below:
GVD(s)
=
VIN
VS
×
1+ sESRCC
1+
s
L
RL
+
s2LC
where,
V – Input voltage
IN
L – Output inductance
R – Load resistance
L
C – Output capacitance
ESR – Output capacitor ESR
C
VS – Peak to peak ramp voltage
2004 Semtech Corp.
8
www.semtech.com
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