SC905AMLTRT データシートの表示（PDF） - Semtech Corporation
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SC905AMLTRT Datasheet PDF : 23 Pages
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SC905A
POWER MANAGEMENT
Applications Information
General Description
The SC905A includes nine low dropout (LDO) voltage
regulators to provide complete power regulation capability for
CDMA handsets or other portable electronic equipment.
Five of the LDOs are designed to be used with analog
circuitry such as audio, radio frequency, or oscillator
circuits. These devices have very low noise levels and high
power supply rejection. The output voltage range for four of
these LDOs, VTCXO, VPLL, VTX and VRX, is 2.75V to 3.1V
in 50mV steps, and for the fifth, VANA, the output voltage
range is 2.55V to 2.9V in 50mV steps. The TCXO LDO has
the additional feature of an external enable, EN_TCXO,
which can be used when timing is critical.
Two other LDOs are general purpose regulators designed
to be used with digital circuits. The noise requirements
for these LDOs are relaxed, but their voltage range is
expanded to cover the wide range of voltages needed for
different types of functions. The outputs for these LDOs
are VCORE and VPAD.
Two other LDOs are general purpose regulators that can be
used with other peripheral circuits. The VMOT and VCAM
outputs can be programmed to supply from 1.75V to 3.3V
in 50mV steps. The VMOT output is specifically designed
to drive a vibrator motor. This output can supply up to
150mA at any of the output voltage settings, allowing
designers the flexibility to select the output voltage that
provides maximum vibration. The VMOT output also has
its own external enable, EN_MOT, to allow greater flexibility.
When not used in conjunction with a vibrator, this output
can be used as a general purpose digital regulator. The
VCAM output is capable of supplying up to 100mA to drive
a digital camera module or any other peripheral circuit
found in a portable application.
Power-On Control
The SC905A is activated when the ON pin is pulled high,
provided that the input voltage is within the specified
operating range. The ON pin responds to logic-high edge
triggering to power up the handset. The rising edge ON
signal is latched when the CORE, PAD, ANA, and TCXO LDOs
are turned on and PGOOD goes high. When the PAD LDO
output voltage reaches 77% of its regulation point, the reset
timer starts and the RESB signal transitions high after delay
of typically 100ms. After a successful power up sequence,
any subsequent condition that toggles RESB (e.g. VPAD
short-circuit, over-temperature, under voltage lockout, I2C
disable of VPAD) will see a delay in the RESB transition
back to high of typically 250ms. The microprocessor then
raises PGOOD high to keep the SC905A powered on. There
is no time limit for the MSM to activate PGOOD. If the MSM
fails to raise PGOOD before the ON switch is released, the
SC905A will transition back into standby mode.
Once the phone is powered on, the SC905A can only be
directly powered off when the PGOOD signal goes low.
Therefore, if the ON pin transitions high when the PGOOD
signal is high, the LDOs and RESB signal will remain in their
state until the microprocessor pulls the PGOOD signal low.
Once the PGOOD signal is low, all the LDOs immediately
power off and all the logic resets to the shutdown condition.
The SC905A can be indirectly powered off by using the I2C
command to turn off the core supply. This will result in a
loss of power to the MSM causing PGOOD to go low, thus
disabling the SC905A.
The HFPWR and CHPWR pins operate identically to the ON
pin. These pins provide alternative sources for activating
power so that remote devices such as battery chargers or
system connector pins can be used to enable the device.
LDO Programmable Output Voltage
The output voltage of each LDO regulator is programmable.
Each LDO has a program voltage register that can be
accessed through the I2C interface and the output voltage
adjusted as necessary. (See the Tables on pages 14, 15
and 16 for more information.)
ON/OFF Control Register
Each individual LDO may be turned on or off by accessing
the ON/OFF control register. LDOs are turned on by setting
their respective on/off bits to 1 and disabled by setting the
on/off bits to 0. This allows for on/off control with a single
write command.
The register data is maintained when an on/off bit is
toggled, but all programmed information will be lost when
the PGOOD input goes low.
It should be noted that the enable signal control from the
I2C for LDOs TCXO and MOT are OR’d with their respective
external enable signals EN_TCXO and EN_MOT. This
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