SCN2652 データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

SCN2652

Multi-protocol communications controller(MPCC)

Philips Electronics 

Philips Semiconductors

Multi-protocol communications controller (MPCC)

Product specification

SCN2652/SCN68652

PIN DESCRIPTION

MNEMONIC

DB15–DB00

A2–A0

PIN NO.

17–10

24–31

19–21

TYPE

I/O

I

NAME AND FUNCTION

Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status

information to or from the processor. Corresponding bits of the high and low order bytes can be wire

OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.

Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or

byte basis. See Register Address section.

BYTE

22

I

Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies

16-bit data bus transfers.

CE

1

I Chip Enable: A high input permits a data bus operation when DBEN is activated.

Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the

R/W

18

I addressed register. A low input causes the contents of the addressed register to be presented on the

data bus.

DBEN

Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,

23

I the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is

loaded into the addressed register and TxBE will be reset if TDSR was addressed.

RESET

33

I Reset: A high level initializes all internal registers (to zero) and timing.

MM

40

I

Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic

purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.

RxE

8

I

Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the

receiver logic and initializes all receiver registers and timing.

Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.

In the BOP mode this character is the address. The received address must match the secondary station

RxA

5

O

address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR13) is set, the first

non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second

SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA

is reset by a low level at RxE.

RxDA*

RxC

6

O

Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to

be presented to the processor. This output is reset when RDSRL is read.

2

I

Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial

data into the RxSR from RxSI.

S/F

4

O SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.

RxSA*

RxSI

7

O

Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSRH

except for RSOM. It is cleared when RDSRH is read.

3

I Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’.

Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At

TxE

37

I the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG

(BOP) or last character (BCP) is output on TxSO.

TxA

34

O

Transmitter Active: TxA is asserted after TSOM (TDSR8) is set and TxE is raised. This output will reset

when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.

TxBE*

35

O

Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control

information or data. The processor should respond by loading theTDSR which resets TxBE.

TxU*

Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been

36

O

delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line

fill depends on PCSAR11. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the

falling edge of TxC.

TxC

39

I

Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts

data out of the TxSR to TxSO.

TxSO

38

O Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.

VCC

32

I

GND

9

I

*Indicates possible interrupt signal

+5V: Power supply.

Ground: 0V reference ground.

1995 May 01

4

Share Link: