SERC816 データシートの表示（PDF） - STMicroelectronics
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SERC816 Datasheet PDF : 23 Pages
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SERCON816
3.3 ELECTRICAL CHARACTERISTCS (continued)
(VDD = 5V ± 5% Tamb = -40 °C to +85 °C, unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
VOL Low level output voltage, pins
TXD6-1, L_ERRN
IOI = -8 mA
0.4
V
VOH High level output voltage, pins
IOH = +8 mA
2.4
TXD6-1, L_ERRN
IOZ Tri-state output leakage
VO = 0 V or VDD
1
µA
IKLU I/O latch-up current
V<VSS V>VDD
200
mA
VESD Electrostatic protection
Leakage < 1 µA, human body
2000
V
model
CPIN Pin capacitance
10
pF
3.4 Power Dissipation
(VDD = 5V ± 5% Tamb = -40 °C to +85 °C, unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
PD Power dissipation
16 Mbaud, MCLK=64 MHz
8501
mW
PDA Maximum allowed power
dissipation
TA=+85°, no air flow
1000 mW
Notes: 1. estimated
3.4.1 Power Dissipation Considerations
Most of the current consumed by CMOS devices is alternate current (AC) which is charging and discharg-
ing the capacitances of the pins and internal nodes. The current consumption rises with the frequency at
which the pins and internal nodes will toggle and with the capacitances connected to the pins of the device:
P = f · C · V2 (C=capacitance, V=voltage, f=frequency)
For applications which require low power consumption or exceeds the maximum allowed power consump-
tion the following is required:
– Connect unused pins to pull-up or pull-down resistors
– Minimize the capacitive load on the pins
– Reduce clock frequency of SCLK and MCLK
– Minimize accesses to the internal RAM and control registers
The maximum allowed power consumption is limited by the maximum allowed chip junction temperature
and by the number of VCC/VDD pins. The chip junction temperature is influenced by the ambient temper-
ature and the package thermal resistance. The ambient temperature could be influenced by the applica-
tion through a good temperature management like heat sinks or ambient air cooling.
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