SH7011 データシートの表示（PDF） - Renesas Electronics

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SH7011

SH7011 Hardware Manual

Renesas Electronics 

Section 5 Exception Processing .................................................................................... 45

5.1 Overview............................................................................................................................ 45

5.1.1 Types of Exception Processing and Priority ........................................................ 45

5.1.2 Exception Processing Operations ......................................................................... 46

5.1.3 Exception Processing Vector Table...................................................................... 47

5.2 Resets................................................................................................................................. 49

5.2.1 Reset ..................................................................................................................... 49

5.2.2 Power-On Reset.................................................................................................... 49

5.3 Address Errors ................................................................................................................... 50

5.3.1 Address Error Exception Processing.................................................................... 50

5.4 Interrupts............................................................................................................................ 51

5.4.1 Interrupt Priority Level......................................................................................... 51

5.4.2 Interrupt Exception Processing ............................................................................ 52

5.5 Exceptions Triggered by Instructions................................................................................ 52

5.5.1 Trap Instructions .................................................................................................. 53

5.5.2 Illegal Slot Instructions ........................................................................................ 53

5.5.3 General Illegal Instructions .................................................................................. 53

5.6 When Exception Sources Are Not Accepted..................................................................... 54

5.6.1 Immediately after a Delayed Branch Instruction.................................................. 54

5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 54

5.7 Stack Status after Exception Processing Ends................................................................... 55

5.8 Notes on Use...................................................................................................................... 56

5.8.1 Value of Stack Pointer (SP).................................................................................. 56

5.8.2 Value of Vector Base Register (VBR) ................................................................. 56

5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 56

Section 6 Interrupt Controller (INTC)......................................................................... 57

6.1 Overview............................................................................................................................ 57

6.1.1 Features ................................................................................................................ 57

6.1.2 Block Diagram...................................................................................................... 58

6.1.3 Pin Configuration ................................................................................................. 59

6.1.4 Register Configuration ......................................................................................... 59

6.2 Interrupt Sources................................................................................................................ 60

6.2.1 NMI Interrupts...................................................................................................... 60

6.2.2 IRQ Interrupts ...................................................................................................... 60

6.2.3 On-Chip Peripheral Module Interrupts ................................................................ 61

6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. 61

6.3 Description of Registers .................................................................................................... 64

6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) .................................................. 64

6.3.2 Interrupt Control Register (ICR) .......................................................................... 65

6.3.3 IRQ Status Register (ISR) .................................................................................... 66

6.4 Interrupt Operation ............................................................................................................ 68

6.4.1 Interrupt Sequence................................................................................................ 68

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