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SI4702-C19 データシートの表示(PDF) - Silicon Laboratories

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SI4702-C19 Datasheet PDF : 46 Pages
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Si4702/03-C19
Table 6. 3-Wire Control Interface Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
SCLK Frequency
fCLK
0
2.5
MHz
SCLK High Time
tHIGH
25
ns
SCLK Low Time
tLOW
25
ns
SDIO Input, SEN to SCLKSetup
tS
20
ns
SDIO Input to SCLKHold
SEN Input to SCLKHold
tHSDIO
tHSEN1
10
ns
10
ns
SEN Input to SCLKHold
tHSEN2
10
ns
SCLKto SDIO Output Valid
tCDV
Read
2
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
25
ns
Note: When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK 70%
30%
tS
SEN 70%
30%
tHSDIO
tS
tHIGH
tLOW
tHSEN1
tHSEN2
SDIO 70%
30%
A6-A5,
A7
R/W,
A0
A4-A1
D15
D14-D1
D0
Address In
Data In
Figure 3. 3-Wire Control Interface Write Timing Parameters
8
Rev. 1.1

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