SI5322 データシートの表示（PDF） - Silicon Laboratories

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SI5322

PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Silicon Laboratories 

Si5322

Pin #

34

35

29

28

7, 18, 19,

20, 36

GND PAD

Pin Name

CKOUT2–

CKOUT2+

CKOUT1–

CKOUT1+

NC

GND

Table 3. Si5322 Pin Descriptions (Continued)

I/O Signal Level

Description

Clock Output 2.

Differential output clock with a frequency selected from a

O

Multi

table of values. Output signal format is selected by SFOUT

pins. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive

identical single-ended clock outputs.

Clock Output 1.

Differential output clock with a frequency selected from a

O

Multi

table of values. Output signal format is selected by SFOUT

pins. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive

identical single-ended clock outputs.

No Connect.

—

—

These pins must be left unconnected for normal operation.

GND

Supply

Ground Pad.

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Preliminary Rev. 0.47

9

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