SIP11205 データシートの表示（PDF） - Vishay Semiconductors

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SIP11205

Feed-Forward Controller with Primary MOSFET Drivers for Intermediate Bus Converters

Vishay Semiconductors 

SiP11205

Vishay Siliconix

Immediate Response to UVLO Faults:

The under voltage protection conditions at converter-level

(VINDET pin UVLO) and chip-level (VCC UVLO) will

immediately trigger a shutdown-and-retry SS response, with

the restart requirements being that:

1. The SS pin has been discharged at a 20 µA rate to the

0.25 V level.

2. The affected supply has recovered to its turn-on

threshold.

Once these conditions are met, switching will resume with a

normal soft-start cycle. Response to UVLO faults is enabled

at all times, including the initial ramp-up period of the soft-

start pin.

Immediate Response to an OTP Condition:

Failure of the application circuit to provide an external

voltage to the VCC pin above the VREG level may result in an

OTP condition (TJ > OTPON). Other conditions, such as

excessive ambient temperature or, where applicable, failure

of airflow over the DC-DC converter circuit, can also trigger

an OTP condition. An OTP condition will immediately trigger

a shutdown-and-retry soft start response, with the restart

requirements being that:

1. The SS pin has been discharged at a 20 µA rate to the

0.25 V level.

2. The chip junction temperature has fallen below the lower

OTP threshold.

Once these conditions are met, switching will resume with a

normal soft-start cycle. Response to the OTP condition is

enabled at all times, including the initial ramp-up period of the

soft-start pin.

Reference

The reference voltage of SiP11205 is set at 3.3 V at VREF

pin. This pin should be decoupled externally with a 0.1 µF to

1 µF capacitor to GND. Up to 5 mA may be drawn internally

from this reference to power external circuits. Note that if the

VINDET pin is pulled below 0.55 V (typical), the reference will

be turned off, and SiP11205 will enter a low-power "standby"

mode. During startup or when VREF is accidentally shorted to

ground, this pin has internal short circuit protection limiting

the source current to 50 mA. VREF load regulation for 5 mA

step is typically 0.45 %.

Oscillator

The oscillator is designed to operate from 200 kHz to 1 MHz

with temperature stability within 15 %. This operating

frequency range allows the converter to minimize the

inductor and capacitor size, improving the power density of

the converter. The oscillator frequency, and therefore the

switching frequency, is programmable by the value of

resistor and capacitor connected to the ROSC and COSC pins

respectively. Note that the switching frequency at pins DL

and DH is half of the oscillator frequency, i.e., the DL output

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will be active during one oscillator cycle, and the DH during

the next oscillator cycle.

The feed-forward voltage appears at pin ROSC and equals to

VINDET/2. This voltage sets the peak voltage of the oscillator

waveform. Therefore the higher input voltage the higher

VINDET/2 and the higher oscillator peak voltage. The pulse

width of the drive signals DL and DH is then generated by

comparing the voltage at RDB pin with the oscillator output

saw tooth. The voltage at RDB pin is fixed so the higher input

voltage the narrower DL/DH pulse width and the lower the

duty cycle. (See Feed-forward Function Diagram.)

VINDET

The VINDET pin controls several modes of operation and the

modes of operation are controlled by shutdown (VSD) and

under voltage (VUV) comparators (see block diagram). When

the IC is powered solely by VIN and VINDET is less than VSDH

due to some external reset condition the pre-regulator is in

low power standby mode and the internal bias network is

powered down. When VINDET is greater than VSDH but less

than VREF and VCC is forced to 12 V the pre-regulator shuts

off drawing only leakage current from VIN and quiescent

current from VCC. In this mode the controller output drivers

remains static (non-switching). When VINDET is above VREF

the controller is enabled and both drivers are switching at half

the oscillator frequency. If SiP11205 is shut down via this pin,

its restart will be by means of a soft-start cycle, as described

under "Soft Start" and "Hiccup-Mode Operation" above.

The input impedance to ground of this pin is typically

46K ± 30 % and must be taken into account when designing

the feed-forward compensation. An external 10:1 resistor

divider ratio of supply voltage to VINDET pin is required in a

typical application.

Primary Side MOSFET Drivers

The low-side MOSFET driver is powered directly from VCC of

the chip. The high-side MOSFET however requires the gate

voltage to be higher than VIN. This is achieved with a charge

pump capacitor CBST between BST and LX, and an external

diode to charge and bootstrap the initial charge up voltage

across CBST to VCC level. On the alternate oscillator cycle

the boost diode isolates BST from VIN and hence BST and

LX steps up to VIN + VCC and VIN, respectively. This

sequencing insures that DL will always turn on before DH

during start-up. The boost capacitor value must be chosen to

meet the application droop rate requirement.

External Frequency Synchronization

The oscillator frequency of this IC can be synchronized to an

external source with a simple circuit shown in "Circuit for

Frequency Synchronization" diagram. The synchronized

frequency should not exceed 1.4 times the set frequency,

and the synchronized frequency range should not exceed

the IC frequency range.

Document Number: 69233

S-81795-Rev. C, 04-Aug-08

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