µ PD16340
TRUTH TABLE
Shift Register Block
Input
R,/L
CLK
H
↑
H
H or L
L
↑
L
H or L
Output
A
Input
Output Note2
Output
B
Output Note1
Output
Input
Shift Register
Right shift operation performed
Hold
Left shift operation performed
Hold
Notes 1. On the rising edge of the clock, the data of S91-S93 (S85-S90) is shifted to S94-S96 (S91-S96), and is output
from B1-B3 (B1-B6) (The parenthesized pins are used in 6-bit input mode.).
2. On the rising edge of the clock, the data of S4-S6 (S7-S12) is shifted to S1-S3 (S1-S6), and is output from
A1-A3 (A1-A6) (The parenthesized pins are used in 6-bit input mode.).
Latch Block
/LE
↓
H or L
Output State of Latch Section (/Ln)
Latch Sn data
Hold latch (output) data
Driver Block
A (B)
/HBLK
/LBLK
HZ
x
L
H
L
x
x
L
L
x
x
x
H
L
H
H
L
H
H
H
L
Remark x : H or L, H : High level, L : Low level
Output State of Driver Block
All driver output : H
All driver output : L
All driver output : High Impedance
L
H
Data Sheet S13685EJ1V0DS00
5