SMH4803AS データシートの表示（PDF） - Summit Microelectronics

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SMH4803AS

Distributed Power Hot Swap Controller

Summit Microelectronics 

SMH4803A

Preliminary

level may be set in steps (up to 15) of 62.5mV below 2.5V.

The default under-voltage hysteresis level is set to

62.5mV.

Soft Start Slew Rate Control

Once all of the preconditions for powering up the DC/DC

controllers have been met, the SMH4803A provides a

means to soft start the external power FET. It is important

to limit in-rush current to prevent damage to the add-in

card or disruptions to the host power supply. For example,

charging the filter capacitance (normally required at the

input of the DC/DC controllers) too quickly may generate

very high current. The VGATE output of the SMH4803A

is current limited to IVGATE, allowing the slew rate to be

easily modified using external passive components. The

slew rate may be found by dividing IVGATE by the gate-to-

drain capacitance placed on the external FET. A complete

design example is given in the Applications Section.

Load Control — Sequencing the Secondary Sup-

plies

Once power has been ramped to the DC/DC controllers,

two conditions must be met before the PGn# outputs can

be enabled: the Drain Sense voltage must be below 2.5V,

and the VGATE voltage must be greater than VDD –VGT.

The Drain Sense input helps ensure that the power MOS-

FET is not absorbing too much steady state power from

operating at a high VDS. This sensor remains active at all

times (except during the current regulation period). The

VGATE sensor makes sure that the power MOSFET is

operating well into its saturation region before allowing the

loads to be switched on. Once VGATE reaches VDD –VGT

this sensor is latched.

Once the external MOSFET is properly switched on the

PGn# outputs may be enabled (if ENPGA and ENPGB are

both high). Output PG1# is activated first, followed by

PG2# after a delay of tPGD, and PG3# after another tPGD

delay. The delays built into the SMH4803A allow timed

sequencing of power to the loads. The delay times are

factory programmed from 50µs to 160ms.

PG2# and PG3# can be disabled by bringing ENPGA low.

Likewise PG#3 is disabled when ENPGB is low. This

cascaded control is useful for enabling supplies that have

dependencies based on the other voltages in the system.

The PGn# outputs have a 12V withstand capability, so

high voltages must not be connected to these pins. Bipolar

transistors or opto-isolators can be used to boost the

withstand voltage to that of the host supply. See Figures

10 and 11 for connections.

Circuit Breaker Operation

The SMH4803A provides a number of circuit breaker

functions to protect against over current conditions. A

sustained over-current event could damage the host sup-

ply and/or the load circuitry. The board’s load current

passes through a series resistor (R ) connected between

S

the MOSFET source (which is tied to CBSENSE) and VSS.

The breaker trips whenever the voltage drop across RS is

greater than 50mV for more than t (a factory program-

CBD

mable filter delay ranging from 10µs to 500µs).

Quick-TripTM Circuit Breaker

Additionally, the SMH4803A provides a Quick-Trip feature

that will cause the circuit breaker to trip immediately if the

voltage drop across RS exceeds VQCB. The Quick-Trip

level may be factory set to 60mV, 100mV (default),

200mV, or the feature may be disabled.

Current Regulation

The current regulation mode is an optional feature that

provides a means to regulate current through the MOS-

FET for a programmable period of time. If enabled the

device will start the internal timer when the voltage at

CBSENSE exceeds 50mV. Also, it attempts to limit the

voltage at CBSENSE to 60mV by regulating the VGATE

output. The circuit breaker will trip if the over-current

condition remains after the time-out. However, if CB-

SENSE drops below 50mV before the timer ends, the

timer is reset and VGATE resumes normal operation. If

the Quick-Trip level is exceeded then the device will

bypass the current regulation timer and shut down imme-

diately. The Current Regulation feature is disabled in the

default configuration.

Non-Volatile Fault Latch

The SMH4803A also provides an optional nonvolatile fault

latch (NVFL) circuit breaker feature. The nonvolatile fault

latch essentially provides a programmable fuse on the

circuit breaker. When enabled the nonvolatile fault latch

will be set whenever the circuit breaker trips. Once set, it

cannot be reset by cycling power or through the use of the

RESET# pin.

NOTE: THE DEVICE REMAINS PERMANENTLY DISABLED

UNTIL IT IS REPROGRAMMED AT THE FACTORY.

As long as the NVFL is set the FAULT# output will be

driven active. The Non-Volatile Fault Latch feature is

disabled in the default configuration.

SUMMIT MICROELECTRONICS, Inc.

2051 4.4 3/15/01

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