SMM150ECR01 データシートの表示（PDF） - Summit Microelectronics
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SMM150ECR01 Datasheet PDF : 22 Pages
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PIN DESCRIPTIONS
SMM150
Preliminary Information
QFN
Pad
Number
28
1
2
4
6
8
10
20
14
21
23
7
24
25
19
12
11
5
3, 9, 13,
15-18,
22, 26,
27, 29
Ultra
CSPTM
Ball
Number
B2
A1
B1
C1
D1
Pin
Type
I/O
I
I
I
I
Pin Name
SDA
SCL
A2
A1
A0
D2
I WP
E2
CAP CAPM
B3
O TRIM
E4
I VM
A4 PWR VDD
A3 PWR VDD_CAP
E1 GND GND
C3
I MUP
A2
I MDN
B4
I COMP1
E3
I COMP2
D3
O FAULT#
C2
I/O READY
C4, D4 NC NC
Pin Description
I2C Bi-directional data line
I2C clock input.
The address pins are biased either to VDD, GND or left floating. This
allows for a total of 21 distinct device addresses. When
communicating with the SMM150 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
Programmable Write Protect active high/low input. When asserted,
writes to the configuration registers and general purpose EE are not
allowed. The WP input is internally tied to VDD with a 50KΩ resistor.
External capacitor input used to filter the VM input, 0.2µF.
Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive sense
line or its’ +Vout pin.
Power supply of the part.
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM150 ground pin should be connected to
the ground of the device under control or to a star point ground. PCB
layout should take into consideration ground drops.
Margin up command input. Asserted high. The MUP input is internally
tied to VDD with a 50KΩ resistor.
Margin down command input. Asserted high. The MDN input is
internally tied to VDD with a 50KΩ resistor.
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the internally
programmable VREF voltage. Each comparator can be independently
programmed to monitor for UV or OV. The monitor level is set
externally with a resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option exists
to disable the FAULT# output while the device is margining.
Programmable active high/low open drain output indicates that VM is
at its set point. When programmed as an active high output, READY
can also be used as an input. When pulled low, it will latch the state of
the comparator inputs.
No Connect. The bottom side metal plate (Pad 29) can be connected
to GND or left floating.
Summit Microelectronics, Inc
2075 2.6 05/13/05
4
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