UT62L5128BS-100LI データシートの表示（PDF） - Utron Technology Inc
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UT62L5128BS-100LI Datasheet PDF : 14 Pages
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UTRON
Preliminary Rev. 0.7
UT62L5128(I)
512K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
CL = 30pF+1TTL , IOH/IOL = -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = -40℃ to 85℃)
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
UT62L5128-55
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
UT62L5128-70
MIN. MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
10
-
UT62L5128-100
MIN. MAX.
100
-
-
100
-
100
-
50
10
-
5
-
-
30
-
30
10
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62L5128-55 UT62L5128-70
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
55
-
70
-
Address Valid to End of Write
tAW
50
-
60
-
Chip Enable to End of Write
tCW
50
-
60
-
Address Set-up Time
tAS
0
-
0
-
Write Pulse Width
tWP
45
-
55
-
Write Recovery Time
tWR
0
-
0
-
Data to Write Time Overlap
tDW
25
-
30
-
Data Hold from End of Write Time
tDH
0
-
0
-
Output Active from End of Write
tOW*
5
-
5
-
Write to Output in High Z
tWHZ*
-
30
-
30
*These parameters are guaranteed by device characterization, but not production tested.
UT62L5128-100
MIN. MAX.
100
-
80
-
80
-
0
-
70
-
0
-
40
-
0
-
5
-
-
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80052
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